sunxi: Add support for UART0 in PB pin group on A83T

On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 0f26cb00f2b108593f914d0b5c41cc6f2c8e8a15..7dfb7f5340dba4c93ff3ba7a67c33221aef613c7 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -76,6 +76,10 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
        sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
+       sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
        sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7af5e295dc31f83bad7fd2b62616f7875340bd2a..a2a9a38dbe7e5ff6adc35394f1ebb32409eed774 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -158,6 +158,7 @@ enum sunxi_gpio_number {
 #define SUN5I_GPB_UART0                2
 #define SUN8I_GPB_UART2                2
 #define SUN8I_A33_GPB_UART0    3
+#define SUN8I_A83T_GPB_UART0   2
 
 #define SUNXI_GPC_NAND         2
 #define SUNXI_GPC_SDC2         3