at91: Update meesc board to new SoC access

* convert meesc board to use c stucture SoC access
* change gpio access to at91_gpio syntax
* moved CONFIG_SYS_HZ below board and cpu defines (purely cosmetic)

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>

diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index 694bd743588fa320aad3e5a25adf6044e07a186d..58ef7be5d08d77f421ea36b51ca9aaefedcb4551 100644 (file)
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -3,7 +3,7 @@
  * Stelian Pop <stelian.pop@leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
- * (C) Copyright 2009
+ * (C) Copyright 2009-2010
  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  * esd electronic system design gmbh <www.esd.eu>
  *
@@ -28,13 +28,13 @@
 
 #include <common.h>
 #include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/io.h>
 #include <netdev.h>
@@ -52,10 +52,10 @@ int get_hw_rev(void)
        if (hw_rev >= 0)
                return hw_rev;
 
-       hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
-       hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
-       hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
-       hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+       hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+       hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+       hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+       hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
 
        if (hw_rev == 15)
                hw_rev = 0;
@@ -67,44 +67,44 @@ int get_hw_rev(void)
 static void meesc_nand_hw_init(void)
 {
        unsigned long csa;
+       at91_smc_t      *smc    = (at91_smc_t *) AT91_SMC0_BASE;
+       at91_matrix_t   *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
 
        /* Enable CS3 */
-       csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-       at91_sys_write(AT91_MATRIX_EBI0CSA,
-               csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+       csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+       writel(csa, &matrix->csa[0]);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
-       at91_sys_write(AT91_SMC_SETUP(3),
-               AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-               AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-               AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-               AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-               AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-       at91_sys_write(AT91_SMC_MODE(3),
-               AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-               AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CONFIG_SYS_NAND_DBW_16
-               AT91_SMC_DBW_16 |
-#else /* CONFIG_SYS_NAND_DBW_8 */
-               AT91_SMC_DBW_8 |
-#endif
-               AT91_SMC_TDF_(2));
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+               &smc->cs[3].pulse);
+
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+               &smc->cs[3].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+               AT91_SMC_MODE_EXNW_DISABLE |
+               AT91_SMC_MODE_DBW_8 |
+               AT91_SMC_MODE_TDF_CYCLE(2),
+               &smc->cs[3].mode);
 
        /* Configure RDY/BSY */
-       at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+       at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
        /* Enable NandFlash */
-       at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+       at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
 #ifdef CONFIG_MACB
 static void meesc_macb_hw_init(void)
 {
+       at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
        /* Enable clock */
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+       writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
        at91_macb_hw_init();
 }
 #endif
@@ -117,26 +117,27 @@ static void meesc_macb_hw_init(void)
  */
 static void meesc_ethercat_hw_init(void)
 {
+       at91_smc_t      *smc1   = (at91_smc_t *) AT91_SMC1_BASE;
+
        /* Configure SMC EBI1_CS0 for EtherCAT */
-       at91_sys_write(AT91_SMC1_SETUP(0),
-               AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-               AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC1_PULSE(0),
-               AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
-               AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
-       at91_sys_write(AT91_SMC1_CYCLE(0),
-               AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
+       writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc1->cs[0].setup);
+       writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+               AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+               &smc1->cs[0].pulse);
+       writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+               &smc1->cs[0].cycle);
        /*
         * Configure behavior at external wait signal, byte-select mode, 16 bit
         * data bus width, none data float wait states and TDF optimization
         */
-       at91_sys_write(AT91_SMC1_MODE(0),
-               AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
-               AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
-               AT91_SMC_TDFMODE);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+               AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+               AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 
        /* Configure RDY/BSY */
-       at91_set_B_periph(AT91_PIN_PE20, 0);    /* EBI1_NWAIT */
+       at91_set_b_periph(AT91_PIO_PORTE, 20, 0);       /* EBI1_NWAIT */
 }
 
 int dram_init(void)
@@ -150,7 +151,7 @@ int board_eth_init(bd_t *bis)
 {
        int rc = 0;
 #ifdef CONFIG_MACB
-       rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+       rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
 #endif
        return rc;
 }
@@ -175,7 +176,7 @@ int checkboard(void)
                gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
                puts("Board: EtherCAN/2 Gateway");
                /* switch on LED1D */
-               at91_set_gpio_output(AT91_PIN_PB12, 1);
+               at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
                break;
        default:
                /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
@@ -222,8 +223,9 @@ u32 get_board_rev(void)
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
-       char *str;
-       char buf[32];
+       char            *str;
+       char            buf[32];
+       at91_pmc_t      *pmc = (at91_pmc_t *) AT91_PMC_BASE;
 
        /*
         * Normally the processor clock has a divisor of 2.
@@ -231,10 +233,9 @@ int misc_init_r(void)
         * Check the user has set environment mdiv to 4 to change the divisor.
         */
        if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
-               at91_sys_write(AT91_PMC_MCKR,
-                       (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
-                       AT91SAM9_PMC_MDIV_4);
-               at91_clock_init(0);
+               writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
+                       AT91SAM9_PMC_MDIV_4, &pmc->mckr);
+               at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
                serial_setbrg();
                /* Notify the user that the clock is not default */
                printf("Setting master clock to %s MHz\n",
@@ -247,10 +248,13 @@ int misc_init_r(void)
 
 int board_init(void)
 {
+       at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
+
        /* Peripheral Clock Enable Register */
-       at91_sys_write(AT91_PMC_PCER,   1 << AT91SAM9263_ID_PIOA |
-                                       1 << AT91SAM9263_ID_PIOB |
-                                       1 << AT91SAM9263_ID_PIOCDE);
+       writel(1 << AT91SAM9263_ID_PIOA |
+               1 << AT91SAM9263_ID_PIOB |
+               1 << AT91SAM9263_ID_PIOCDE,
+               &pmc->pcer);
 
        /* initialize ET1100 Controller */
        meesc_ethercat_hw_init();

diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index dad0bef118f614626b9e9126d7bff8589966e172..eaea1cd9c3a67aa5351bdbdbb20e56dcb9546c61 100644 (file)
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -31,14 +31,12 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
 /* Common stuff */
-#define CONFIG_SYS_HZ                  1000    /* decrementer freq */
 #define CONFIG_MEESC                   1       /* Board is esd MEESC */
 #define CONFIG_ARM926EJS               1       /* This is an ARM926EJS Core */
 #define CONFIG_AT91SAM9263             1       /* It's an AT91SAM9263 SoC */
 #define CONFIG_SYS_AT91_MAIN_CLOCK     16000000/* 16.0 MHz crystal */
+#define CONFIG_SYS_HZ                  1000    /* decrementer freq */
 #define CONFIG_DISPLAY_BOARDINFO       1
 #define CONFIG_DISPLAY_CPUINFO         1       /* display cpu info and speed */
 #define CONFIG_PREBOOT                         /* enable preboot variable */
@@ -122,9 +120,9 @@
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PA22
-
+#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN              AT91_PIO_PORTA, 22
+#define CONFIG_SYS_64BIT_VSPRINTF              /* needed for nand_util.c */
 #endif
 
 /* Ethernet */