imx8mp_evk: Update LPDDR4 refresh time

Use more safer refresh time value for 6GB LPDDR4 on this EVK board.
Update the parameters for every frequency point.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index eff0a938601bebf724c4754e84d62dbec4394e58..0759502ba3f60c47fb4fe3045d4e8f72c8d648de 100644 (file)
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -13,7 +13,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400000, 0xa3080020 },
        { 0x3d400020, 0x1323 },
        { 0x3d400024, 0x1e84800 },
-       { 0x3d400064, 0x7a0118 },
+       { 0x3d400064, 0x7a017c },
 #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
        { 0x3d400070, 0x1027f54 },
 #else
@@ -35,7 +35,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d40011c, 0x501 },
        { 0x3d400130, 0x20800 },
        { 0x3d400134, 0xe100002 },
-       { 0x3d400138, 0x120 },
+       { 0x3d400138, 0x184 },
        { 0x3d400144, 0xc80064 },
        { 0x3d400180, 0x3e8001e },
        { 0x3d400184, 0x3207a12 },
@@ -82,7 +82,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402020, 0x1021 },
        { 0x3d402024, 0x30d400 },
        { 0x3d402050, 0x20d000 },
-       { 0x3d402064, 0xc001c },
+       { 0x3d402064, 0xc0026 },
        { 0x3d4020dc, 0x840000 },
        { 0x3d4020e0, 0x330000 },
        { 0x3d4020e8, 0x660048 },
@@ -97,7 +97,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d40211c, 0x301 },
        { 0x3d402130, 0x20300 },
        { 0x3d402134, 0xa100002 },
-       { 0x3d402138, 0x1d },
+       { 0x3d402138, 0x27 },
        { 0x3d402144, 0x14000a },
        { 0x3d402180, 0x640004 },
        { 0x3d402190, 0x3818200 },
@@ -107,7 +107,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403020, 0x1021 },
        { 0x3d403024, 0xc3500 },
        { 0x3d403050, 0x20d000 },
-       { 0x3d403064, 0x30007 },
+       { 0x3d403064, 0x3000a },
        { 0x3d4030dc, 0x840000 },
        { 0x3d4030e0, 0x330000 },
        { 0x3d4030e8, 0x660048 },
@@ -122,7 +122,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d40311c, 0x301 },
        { 0x3d403130, 0x20300 },
        { 0x3d403134, 0xa100002 },
-       { 0x3d403138, 0x8 },
+       { 0x3d403138, 0xa },
        { 0x3d403144, 0x50003 },
        { 0x3d403180, 0x190004 },
        { 0x3d403190, 0x3818200 },