ARM: DRA7: Enable clocks for USB OTGSS and USB PHY

Enabled clocks for dwc3 controller and USB PHY present in DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index b9734fea8febaea9cf3cd805c4090a038d5337e0..e4abb25fc2430acc2917dd9a66a72c5de7092ebc 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -460,6 +460,10 @@ void enable_basic_clocks(void)
                (*prcm)->cm_l4per_gpio6_clkctrl,
                (*prcm)->cm_l4per_gpio7_clkctrl,
                (*prcm)->cm_l4per_gpio8_clkctrl,
+#ifdef CONFIG_USB_DWC3
+               (*prcm)->cm_l3init_ocp2scp1_clkctrl,
+               (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+#endif
                0
        };
 
@@ -491,6 +495,16 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
 
+#ifdef CONFIG_USB_DWC3
+       /* Enable 960 MHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+                    OPTFCLKEN_REFCLK960M);
+
+       /* Enable 32 KHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+#endif
+
        /* Set the correct clock dividers for mmc */
        setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_DIV_MASK);

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 0745d424e2c4803cb1c7db082c1b0983ee004885..440bb40a14c05ed345d8ff42c5553271fc465151 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -575,7 +575,7 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_div_m2_dpll_unipro = 0x4a0081d0,
        .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
        .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
-       .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
+       .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640,
        .cm_coreaon_bandgap_clkctrl = 0x4a008648,
        .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
 
@@ -709,7 +709,7 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
        .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
        .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
-       .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
+       .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
 
        /* prm irqstatus regs */
        .prm_irqstatus_mpu_2 = 0x4ae06014,
@@ -801,8 +801,8 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_clkmode_dpll_dsp                    = 0x4a005234,
        .cm_shadow_freq_config1                 = 0x4a005260,
        .cm_clkmode_dpll_gmac                   = 0x4a0052a8,
-       .cm_coreaon_usb_phy_core_clkctrl        = 0x4a008640,
-       .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
+       .cm_coreaon_usb_phy1_core_clkctrl       = 0x4a008640,
+       .cm_coreaon_usb_phy2_core_clkctrl       = 0x4a008688,
 
        /* cm1.mpu */
        .cm_mpu_mpu_clkctrl                     = 0x4a005320,
@@ -908,7 +908,7 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_gmac_gmac_clkctrl                   = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
        .cm_l3init_ocp2scp3_clkctrl             = 0x4a0093e8,
-       .cm_l3init_usb_otg_ss_clkctrl           = 0x4a0093f0,
+       .cm_l3init_usb_otg_ss1_clkctrl          = 0x4a0093f0,
 
        /* cm2.l4per */
        .cm_l4per_clkstctrl                     = 0x4a009700,

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 123c84ff95936280b5dff115400d1eba9ef0c9d0..c8c3e71b55395b587e343b715eddc4fce28c3f7e 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -143,7 +143,7 @@ struct prcm_regs {
        u32 cm_div_m2_dpll_unipro;
        u32 cm_ssc_deltamstep_dpll_unipro;
        u32 cm_ssc_modfreqdiv_dpll_unipro;
-       u32 cm_coreaon_usb_phy_core_clkctrl;
+       u32 cm_coreaon_usb_phy1_core_clkctrl;
        u32 cm_coreaon_usb_phy2_core_clkctrl;
 
        /* cm2.core */
@@ -230,7 +230,7 @@ struct prcm_regs {
        u32 cm_l3init_fsusb_clkctrl;
        u32 cm_l3init_ocp2scp1_clkctrl;
        u32 cm_l3init_ocp2scp3_clkctrl;
-       u32 cm_l3init_usb_otg_ss_clkctrl;
+       u32 cm_l3init_usb_otg_ss1_clkctrl;
 
        u32 prm_irqstatus_mpu_2;