sunxi: rsb: Add sun9i (A80 support)

Add support for the A80 to the rsb code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 1c4b7633f92308b28fb48ef5df9e29888cacb052..48db7442f4f0b771a6f1865a611aa9cb45975d3d 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -15,8 +15,10 @@ obj-y        += pinmux.o
 obj-y  += usbc.o
 obj-$(CONFIG_MACH_SUN6I)       += prcm.o
 obj-$(CONFIG_MACH_SUN8I)       += prcm.o
+obj-$(CONFIG_MACH_SUN9I)       += prcm.o
 obj-$(CONFIG_MACH_SUN6I)       += p2wi.o
 obj-$(CONFIG_MACH_SUN8I)       += rsb.o
+obj-$(CONFIG_MACH_SUN9I)       += rsb.o
 obj-$(CONFIG_MACH_SUN4I)       += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)       += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)       += clock_sun6i.o

diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index b72bb9db519f18f3b27d79f939c07a183061ece8..55e943323f8e12f0a489a3af3bf4f70846b840d7 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -18,12 +18,23 @@
 
 static void rsb_cfg_io(void)
 {
+#ifdef CONFIG_MACH_SUN8I
        sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
        sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
        sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
        sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
        sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
        sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+       sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
+       sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
+       sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+       sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+       sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+       sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
 }
 
 static void rsb_set_clk(void)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index a2a7839c6bdfcf014710e697eef6b66f8dde9f33..04889c51fac51076f0aae3b1ea148df45b05194b 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -73,7 +73,6 @@
 #define SUNXI_CCM_BASE                 (REGS_APB0_BASE + 0x0000)
 #define SUNXI_CCMMODULE_BASE           (REGS_APB0_BASE + 0x0400)
 #define SUNXI_PIO_BASE                 (REGS_APB0_BASE + 0x0800)
-#define SUNXI_R_PIO_BASE               (0x08002C00)
 #define SUNXI_TIMER_BASE               (REGS_APB0_BASE + 0x0C00)
 #define SUNXI_PWM_BASE                 (REGS_APB0_BASE + 0x1400)
 #define SUNXI_LRADC_BASE               (REGS_APB0_BASE + 0x1800)
@@ -92,8 +91,10 @@
 #define SUNXI_TWI4_BASE                        (REGS_APB1_BASE + 0x3800)
 
 /* RCPUS Module */
-#define SUNXI_RPRCM_BASE               (REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_PRCM_BASE                        (REGS_RCPUS_BASE + 0x1400)
 #define SUNXI_R_UART_BASE              (REGS_RCPUS_BASE + 0x2800)
+#define SUNXI_R_PIO_BASE               (REGS_RCPUS_BASE + 0x2c00)
+#define SUNXI_RSB_BASE                 (REGS_RCPUS_BASE + 0x3400)
 
 /* Misc. */
 #define SUNXI_BROM_BASE                        0xFFFF0000 /* 32K */

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 71cc879c2bb0ebf77e2dd7da5b7a6ee3b668ba12..f2c247d79fc7ee68de1bc32e3272c2da561b4965 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -45,9 +45,13 @@
  *
  * sun8i has 1 bank:
  * PL0 - PL11
+ *
+ * sun9i has 3 banks:
+ * PL0 - PL9  | PM0 - PM15  | PN0 - PN1
  */
 #define SUNXI_GPIO_L   11
 #define SUNXI_GPIO_M   12
+#define SUNXI_GPIO_N   13
 
 struct sunxi_gpio {
        u32 cfg[4];
@@ -114,6 +118,7 @@ enum sunxi_gpio_number {
        SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
        SUNXI_GPIO_L_START = 352,
        SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+       SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
        SUNXI_GPIO_AXP0_START = 1024,
 };
 
@@ -129,6 +134,7 @@ enum sunxi_gpio_number {
 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
 #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
 #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
 
 #define SUNXI_GPAXP0(_nr)      (SUNXI_GPIO_AXP0_START + (_nr))
 
@@ -187,6 +193,9 @@ enum sunxi_gpio_number {
 #define SUN8I_GPL2_R_UART_TX   2
 #define SUN8I_GPL3_R_UART_RX   2
 
+#define SUN9I_GPN0_R_RSB_SCK   3
+#define SUN9I_GPN1_R_RSB_SDA    3
+
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE        0
 #define SUNXI_GPIO_PULL_UP     1