powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPL

Enable p1_p2_rdb_pc to start from eSPI with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>

diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 5b8e0ffa6dea6afc63d110b336cdce8a3c3331df..07fab463491c520e87c6c5a47601ba449a8133e8 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -11,6 +11,7 @@
 #include <nand.h>
 #include <i2c.h>
 #include <fsl_esdhc.h>
+#include <spi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,6 +40,10 @@ void board_init_f(ulong bootflag)
        /* Read back the register to synchronize the write. */
        in_be32(&gur->pmuxcr);
 
+#ifdef CONFIG_SPL_SPI_BOOT
+       clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
        /* initialize selected port with appropriate baud rate */
        plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
        plat_ratio >>= 1;
@@ -49,6 +54,8 @@ void board_init_f(ulong bootflag)
                     bus_clk / 16 / CONFIG_BAUDRATE);
 #ifdef CONFIG_SPL_MMC_BOOT
        puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       puts("\nSPI Flash boot...\n");
 #endif
 
        /* copy code to RAM and jump to it - this should not return */
@@ -94,5 +101,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       spi_boot();
 #endif
 }

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 19a1699fd90c3d5d3be1a8dda0da74cad519b5ea..35d674665b4d31278beeaaee9ba326da40f68129 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -174,11 +174,33 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE           0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE           0x11001000
+#define CONFIG_SPL_TEXT_BASE           0xf8f81000
+#define CONFIG_SPL_PAD_TO              0x18000
+#define CONFIG_SPL_MAX_SIZE            (96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_NAND
@@ -544,7 +566,7 @@
  * Config the L2 Cache as L2 SRAM
 */
 #if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_INIT_L2_ADDR                0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
@@ -764,7 +786,7 @@
 /*
  * Environment
  */
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS     0
 #define CONFIG_ENV_SPI_CS      0