CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
-- IDE Reset method:
- CONFIG_IDE_RESET - is this is defined, IDE Reset will
- be performed by calling the function
- ide_set_reset(int reset)
- which has to be defined in a board specific file
-
-- ATAPI Support:
- CONFIG_ATAPI
-
- Set this to enable ATAPI support.
-
- LBA48 Support
CONFIG_LBA48
#ifdef CONFIG_IDE
#define __io
/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 2
/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
#endif /* CONFIG_IDE */
/* Use common timer */
CONFIG_MAC_PARTITION=y
CONFIG_ENV_ADDR=0xFF804000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0xA0
+CONFIG_SYS_ATA_REG_OFFSET=0xA0
+CONFIG_SYS_ATA_ALT_OFFSET=0xC0
+CONFIG_SYS_ATA_IDE0_OFFSET=0
+CONFIG_ATAPI=y
+CONFIG_IDE_RESET=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x280
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_ADDR=0x3D0000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFF84000
CONFIG_NETCONSOLE=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_IDE_MAXDEVICE=1
+CONFIG_SYS_ATA_BASE_ADDR=0xf1080000
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x4000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
CONFIG_CPU=y
CONFIG_NVME=y
CONFIG_SPL_DM_RTC=y
CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
CONFIG_CPU=y
CONFIG_NVME=y
CONFIG_SPI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xA0040000
CONFIG_DM=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_IDE_MAXDEVICE=1
+CONFIG_SYS_ATA_BASE_ADDR=0xb4000000
+CONFIG_SYS_ATA_STRIDE=2
+CONFIG_SYS_ATA_DATA_OFFSET=0x1000
+CONFIG_SYS_ATA_REG_OFFSET=0x1000
+CONFIG_SYS_ATA_ALT_OFFSET=0x800
+CONFIG_IDE_RESET=y
CONFIG_CLK=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_ADC_SANDBOX=y
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_ADC_SANDBOX=y
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_RTC=y
CONFIG_ADC_SANDBOX=y
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CPU=y
CONFIG_ADC_SANDBOX=y
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CPU=y
This allows access to raw blocks and filesystems on an IDE drive
from U-Boot. See also CMD_IDE which provides an 'ide' command for
performing various IDE operations.
+
+if IDE
+
+config SYS_IDE_MAXBUS
+ hex "Maximumm number of IDE buses"
+ default 2
+ help
+ This is the number of IDE buses provided by the board. Each one
+ can have one or two devices. One is designated the master and the
+ other one the slave. It is not required to have one or both on any
+ controller.
+
+config SYS_IDE_MAXDEVICE
+ hex "Maximum number of IDE devices"
+ default 2
+ help
+ This is the number of IDE devices which can be connected to the
+ board. Normally this is 2 * CONFIG_SYS_IDE_MAXBUS since up to two
+ devices can be connected to each bus. The number of devices actually
+ connected is determined by probing.
+
+config SYS_ATA_BASE_ADDR
+ hex "Base address of IDE controller"
+ default 0
+ help
+ This is the address of the IDE controller, from which other addresses
+ are calculated. Each bus is at a fixed offset from this address,
+ so it assumed that they are in the same area of the I/O space or
+ memory.
+
+config SYS_ATA_STRIDE
+ hex "IDE port stride"
+ default 0x1
+ help
+ This is the distance between each IDE register, in bytes. For an
+ 8-bit controller this is typically 1, meaning that the registers
+ appear at consecutive bytes. If the value 2 two, that might indicate
+ a 16-bit register space.
+
+config SYS_ATA_DATA_OFFSET
+ hex "Offset of the data register"
+ default 0x0
+ help
+ This is the offset of the controller's data register from the base
+ address of the controller. This is typically 0, but may be something
+ else if there are some other registers at the start of the
+ controller space.
+
+config SYS_ATA_REG_OFFSET
+ hex "Offset of the register space"
+ default 0x0
+ help
+ This is the offset of the controller's 'register' space from the base
+ address of the controller. The data register (which is typically at
+ offset 0) has its own CONFIG, to deal with controllers where it is
+ somewhere else. Register 1 will be at this offset + 1, register 2 at
+ CONFIG_SYS_ATA_REG_OFFSET + 2, etc.
+
+config SYS_ATA_ALT_OFFSET
+ hex "Offset of the alternative registers"
+ default 0x0
+ help
+ This is the offset of the controller's 'alternative' space from the
+ base address of the controller. This allows these registers to be
+ located separately from the data and register space.
+
+config SYS_ATA_IDE0_OFFSET
+ hex "Offset of bus 0"
+ default 0x1f0
+ help
+ This is the start offset of bus 0 from the start of the
+ controller registers. All the other registers are calculated from
+ this address. using the above options. For x86 hardware this is often
+ 0x1f0.
+
+config SYS_ATA_IDE1_OFFSET
+ hex "Offset of bus 1"
+ default 0x170
+ help
+ This is the start offset of bus 1 from the start of the
+ controller registers. All the other registers are calculated from
+ this address. using the above options. For x86 hardware this is often
+ 0x170.
+
+config ATAPI
+ bool "Enable ATAPI support"
+ help
+ This enabled Advanced Technology Attachment Packet Interface (ATAPI),
+ a protocol that allows a greater variety of devices to be connected
+ to the IDE port than with plain ATA. It allows SCSI commands to be
+ sent across the bus, e.g. to support optical drives.
+
+config IDE_RESET
+ bool "Support board-specific reset"
+ help
+ If this is defined, IDE Reset will be performed by calling the
+ function:
+
+ ide_set_reset(int reset)
+
+ where reset is 1 to assert reset and 0 to de-assert it. This function
+ must be defined in a board-specific file.
+
+endif # IDE
* 8-bit (register) and 16-bit (data) accesses might use different
* address spaces. This is implemented by the following definitions.
*/
-#ifndef CONFIG_SYS_ATA_STRIDE
-#define CONFIG_SYS_ATA_STRIDE 1
-#endif
#define ATA_IO_DATA(x) (CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
#define ATA_IO_REG(x) (CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
#ifdef CONFIG_IDE
/* ATA */
-# define CONFIG_IDE_RESET 1
# define CONFIG_IDE_PREINIT 1
-# define CONFIG_ATAPI
# undef CONFIG_LBA48
-
-# define CONFIG_SYS_IDE_MAXBUS 1
-# define CONFIG_SYS_IDE_MAXDEVICE 2
-
-# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
-# define CONFIG_SYS_ATA_IDE0_OFFSET 0
-
-# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
-# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
-# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
-# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
#endif
#define CONFIG_DRIVER_DM9000
"stderr=serial,vidconsole\0"
/* ATA/IDE support */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_ATAPI
#endif /* __CONFIG_H */
#ifdef CONFIG_IDE
#define __io
/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
/* end of IDE defines */
#endif /* CMD_IDE */
"stderr=serial,vidconsole\0"
/* ATA/IDE support */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_ATAPI
#endif /* __CONFIG_H */
*/
#ifdef CONFIG_IDE
#define __io
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_IDE */
#endif /* _CONFIG_IB62x0_H */
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_SYS_IDE_MAXBUS
-#undef CONFIG_SYS_IDE_MAXDEVICE
/*
* Enable platform initialisation via misc_init_r() function
/*
* IDE/ATA
*/
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
/*
* Commands
/*
* SATA Driver configuration
*/
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_OPENRD_BASE_H */
* - Only legacy IDE controller is supported for QEMU '-M pc' target
* - AHCI controller is supported for QEMU '-M q35' target
*/
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_ATAPI
#define CONFIG_SPL_BOARD_LOAD_IMAGE
/*
* IDE support
*/
-#define CONFIG_IDE_RESET 1
#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
/*
* SuperH PCI Bridge Configration
#define CONFIG_SANDBOX_SDL
#endif
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_ATA_BASE_ADDR 0x100
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 1
-#define CONFIG_SYS_ATA_ALT_OFFSET 2
-#define CONFIG_SYS_ATA_STRIDE 4
-#endif
-
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_DEVICE 2
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
CONFIG_AT91_GPIO_PULLUP
CONFIG_AT91_LED
CONFIG_AT91_WANTS_COMMON_PHY
-CONFIG_ATAPI
CONFIG_ATMEL_LCD
CONFIG_ATMEL_LCD_BGR555
CONFIG_ATMEL_LCD_RGB565
CONFIG_ICACHE
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
-CONFIG_IDE_RESET
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
CONFIG_SYS_AT91_PLLA
CONFIG_SYS_AT91_PLLB
CONFIG_SYS_AT91_SLOW_CLOCK
-CONFIG_SYS_ATA_ALT_OFFSET
-CONFIG_SYS_ATA_BASE_ADDR
-CONFIG_SYS_ATA_DATA_OFFSET
-CONFIG_SYS_ATA_IDE0_OFFSET
-CONFIG_SYS_ATA_IDE1_OFFSET
-CONFIG_SYS_ATA_REG_OFFSET
-CONFIG_SYS_ATA_STRIDE
CONFIG_SYS_AUTOLOAD
CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
CONFIG_SYS_AUXCORE_BOOTDATA
CONFIG_SYS_I2C_TCA642X_ADDR
CONFIG_SYS_I2C_TCA642X_BUS_NUM
CONFIG_SYS_ICACHE_INV
-CONFIG_SYS_IDE_MAXBUS
-CONFIG_SYS_IDE_MAXDEVICE
CONFIG_SYS_IFC_ADDR
CONFIG_SYS_IFC_CCR
CONFIG_SYS_INIT_DBCR