]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
powerpc: Enable device tree support for P1010RDB
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Fri, 1 May 2020 11:06:26 +0000 (19:06 +0800)
committerPriyanka Jain <priyanka.jain@nxp.com>
Mon, 4 May 2020 03:42:37 +0000 (09:12 +0530)
Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
25 files changed:
arch/powerpc/dts/Makefile
arch/powerpc/dts/p1010rdb-pa.dts [new file with mode: 0644]
arch/powerpc/dts/p1010rdb-pa_36b.dts [new file with mode: 0644]
arch/powerpc/dts/p1010rdb-pb.dts [new file with mode: 0644]
arch/powerpc/dts/p1010rdb-pb_36b.dts [new file with mode: 0644]
arch/powerpc/dts/p1010rdb_32b.dtsi [new file with mode: 0644]
arch/powerpc/dts/p1010rdb_36b.dtsi [new file with mode: 0644]
arch/powerpc/dts/p1010si-post.dtsi [new file with mode: 0644]
arch/powerpc/dts/p1010si-pre.dtsi [new file with mode: 0644]
configs/P1010RDB-PA_36BIT_NAND_defconfig
configs/P1010RDB-PA_36BIT_NOR_defconfig
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PA_NAND_defconfig
configs/P1010RDB-PA_NOR_defconfig
configs/P1010RDB-PA_SDCARD_defconfig
configs/P1010RDB-PA_SPIFLASH_defconfig
configs/P1010RDB-PB_36BIT_NAND_defconfig
configs/P1010RDB-PB_36BIT_NOR_defconfig
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PB_NAND_defconfig
configs/P1010RDB-PB_NOR_defconfig
configs/P1010RDB-PB_SDCARD_defconfig
configs/P1010RDB-PB_SPIFLASH_defconfig

index 3195351c9c38ef29fe7adaf85fb69c8718c92f52..7eb005f45014048b08c18a8382146f6a10864af3 100644 (file)
@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
+dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
+dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
 dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
 dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
 dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
new file mode 100644 (file)
index 0000000..c66c492
--- /dev/null
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+       model = "fsl,P1010RDB";
+       compatible = "fsl,P1010RDB";
+
+       /include/ "p1010rdb_32b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts
new file mode 100644 (file)
index 0000000..b943de7
--- /dev/null
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+       model = "fsl,P1010RDB";
+       compatible = "fsl,P1010RDB";
+
+       /include/ "p1010rdb_36b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts
new file mode 100644 (file)
index 0000000..2675d5d
--- /dev/null
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+       model = "fsl,P1010RDB-PB";
+       compatible = "fsl,P1010RDB-PB";
+
+       /include/ "p1010rdb_32b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts
new file mode 100644 (file)
index 0000000..45ccf91
--- /dev/null
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+       model = "fsl,P1010RDB-PB";
+       compatible = "fsl,P1010RDB-PB";
+
+       /include/ "p1010rdb_36b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb_32b.dtsi b/arch/powerpc/dts/p1010rdb_32b.dtsi
new file mode 100644 (file)
index 0000000..5da790d
--- /dev/null
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+soc: soc@ffe00000 {
+       ranges = <0x0 0x0 0xffe00000 0x100000>;
+};
+
+pci1: pcie@ffe09000 {
+       reg = <0 0xffe09000 0 0x1000>;
+       ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+};
+
+pci0: pcie@ffe0a000 {
+       reg = <0 0xffe0a000 0 0x1000>;
+       ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+};
diff --git a/arch/powerpc/dts/p1010rdb_36b.dtsi b/arch/powerpc/dts/p1010rdb_36b.dtsi
new file mode 100644 (file)
index 0000000..54dd16e
--- /dev/null
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2020 NXP
+ */
+
+soc: soc@fffe00000 {
+       ranges = <0x0 0xf 0xffe00000 0x100000>;
+};
+
+pci1: pcie@fffe09000 {
+       reg = <0xf 0xffe09000 0 0x1000>;
+       ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+};
+
+pci0: pcie@fffe0a000 {
+       reg = <0xf 0xffe0a000 0 0x1000>;
+       ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+};
diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
new file mode 100644 (file)
index 0000000..e24b5e4
--- /dev/null
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2020 NXP
+ */
+
+&soc {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       device_type = "soc";
+       compatible = "fsl,p1010-immr", "simple-bus";
+       bus-frequency = <0>;
+
+       mpic: pic@40000 {
+               interrupt-controller;
+               #address-cells = <0>;
+               #interrupt-cells = <4>;
+               reg = <0x40000 0x40000>;
+               compatible = "fsl,mpic";
+               device_type = "open-pic";
+               big-endian;
+               single-cpu-affinity;
+               last-interrupt-source = <255>;
+       };
+};
+
+/* controller at 0x9000 */
+&pci1 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <1>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+       law_trgt_if = <2>;
+       #address-cells = <3>;
+       #size-cells = <2>;
+       device_type = "pci";
+       bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p1010si-pre.dtsi b/arch/powerpc/dts/p1010si-pre.dtsi
new file mode 100644 (file)
index 0000000..9d7bb6c
--- /dev/null
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+       compatible = "fsl,P1010";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&mpic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,P1010@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+               };
+       };
+};
index 85b97d1e15fafd31c2d22210c546d5aa73f56627..b0dd5f8f7e6cf9984b9e81f54fbc445605d5f7d4 100644 (file)
@@ -10,6 +10,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -76,6 +78,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index e1109637c131d4db3890a347c9da1688753842d0..93042f8cc8f09f431b0479a189a71ff28a374663 100644 (file)
@@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -57,6 +60,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 4b8ddd997c221ffe6287eca0d759f0cdca99bf5b..657b10033b6157857332b39008fbd14166b07d63 100644 (file)
@@ -11,6 +11,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -70,6 +72,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 2975f404fcd1d3bf35ca64ce4d89f558c2b92b86..396921722daaf46441f7d430cf03bc5241757120 100644 (file)
@@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -72,6 +74,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 632ecd7af54376c47bc08227d1dbb9560ce94258..b080bb726be1bee2b3e034e97f6582dc20b65068 100644 (file)
@@ -10,6 +10,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
+CONFIG_OF_CONTROL=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -75,6 +77,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 037fe0ab890ef72682ba068d3bfc1db19f2c5444..a5296a53a5c2321fda9c9ca20afe554a89d9d301 100644 (file)
@@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
+CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -56,6 +59,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 48a1d34cc9a9925352bcd07cc29f3c05f24b14ea..1df83cefe3d953595c9b8c01cc5d8b5550e4e741 100644 (file)
@@ -11,6 +11,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
+CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -69,6 +71,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index f43c60011ce36179bfc533514ba4bc84d7948f29..6bff366f817b27360bfb62711df0e1b8ec6e984c 100644 (file)
@@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
+CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -71,6 +73,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index dd7d68916331d7791f4da65becacf4cd3e5a9788..abf8882f21d31adeaf33f5c9cfa8e2de35d5b65e 100644 (file)
@@ -10,6 +10,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -76,6 +78,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 7e8c150603e82b0d61055b739aaf4fd98ac699a3..beb8f098c490ffb97eee3ece83eddc991e76f8eb 100644 (file)
@@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -57,6 +60,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 7996490e9365b8bbb2a046c4d5a4d9d27a1d849a..7244dacec0bcb4a1acc1e3c64462bfe98a8db8c9 100644 (file)
@@ -11,6 +11,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -70,6 +72,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 4291002d34371748fd3e18a4a36c069084ed39fd..1d40aa054b874ad41f861c8982fdd63eeeb80a72 100644 (file)
@@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -72,6 +74,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 4a216dd55bccf62be710993c01dd07e9b82bd656..0d9df36ea1f15ace1e378e8fa5b445f4a9574432 100644 (file)
@@ -10,6 +10,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
+CONFIG_OF_CONTROL=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 CONFIG_FIT=y
@@ -75,6 +77,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index 2cc52ed76de465a2c1da9c68fd1f68cf36f3a535..653c89bfdd4634e78652daa2236938f52348ee55 100644 (file)
@@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
+CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -56,6 +59,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index d90cc8e7bbf790e28e148f206c347ede25409dad..7bc05e57baa277a38d545a0c54b00f1ec28ddd69 100644 (file)
@@ -11,6 +11,8 @@ CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
+CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -69,6 +71,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y
index e6833d43e3547a0d117179b5b841c6ecbe177516..16976e4a881a67115d5e985d4d0cbcfa1b52df84 100644 (file)
@@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0xD0001000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
+CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -71,6 +73,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_DM_I2C=y
 CONFIG_DM_RTC=y