mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568

Adjust tap number for transmit clock, tap number and delay number for
strobe input to fix HS400 modes on RK3568.

New values have been picked from vendor kernel and u-boot and have
successfully been tested with rock-3a-rk3568_defconfig and

  CONFIG_MMC_HS200_SUPPORT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_HS400_ES_SUPPORT=y
  CONFIG_MMC_SPEED_MODE_SET=y

using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,

  => mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000

for each of the modes below.

  0 = MMC legacy
  1 = MMC High Speed (26MHz)
  3 = MMC High Speed (52MHz)
  4 = MMC DDR52 (52MHz)
  10 = HS200 (200MHz)
  11 = HS400 (200MHz)
  12 = HS400ES (200MHz)

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index bcf65e09174157b4d58c301cb8bdda19e47b7bc1..12a616d3dfb8738ed8926528d72030ab30f7b274 100644 (file)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -69,13 +69,13 @@
 #define DWCMSHC_EMMC_DLL_DLYENA                BIT(27)
 #define DLL_RXCLK_NO_INVERTER          BIT(29)
 #define DLL_RXCLK_ORI_GATE             BIT(31)
-#define DLL_TXCLK_TAPNUM_DEFAULT       0xA
+#define DLL_TXCLK_TAPNUM_DEFAULT       0x10
 #define DLL_TXCLK_TAPNUM_FROM_SW       BIT(24)
-#define DLL_STRBIN_TAPNUM_DEFAULT      0x8
+#define DLL_STRBIN_TAPNUM_DEFAULT      0x4
 #define DLL_STRBIN_TAPNUM_FROM_SW      BIT(24)
 #define DLL_STRBIN_DELAY_NUM_SEL       BIT(26)
 #define DLL_STRBIN_DELAY_NUM_OFFSET    16
-#define DLL_STRBIN_DELAY_NUM_DEFAULT   0x16
+#define DLL_STRBIN_DELAY_NUM_DEFAULT   0x10
 
 #define DLL_LOCK_WO_TMOUT(x) \
        ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \