#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
+#define MMAP_SCM2 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
-
-/*********************************************************************
-* ATA
-*********************************************************************/
-
+#define MMAP_USBHW 0xFC0B0000
+#define MMAP_USBCAPS 0xFC0B0100
+#define MMAP_USBEHCI 0xFC0B0140
+#define MMAP_USBOTG 0xFC0B01A0
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/ssi.h>
+
+/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 rsvd6[106];
} atac_t;
-/*********************************************************************
-* Cross-bar switch (XBS)
-*********************************************************************/
-
-typedef struct xbs {
- u8 resv0[0x100];
- u32 prs1; /* XBS Priority Register */
- u8 resv1[0xC];
- u32 crs1; /* XBS Control Register */
- u8 resv2[0xEC];
- u32 prs2; /* XBS Priority Register */
- u8 resv3[0xC];
- u32 crs2; /* XBS Control Register */
- u8 resv4[0xEC];
- u32 prs3; /* XBS Priority Register */
- u8 resv5[0xC];
- u32 crs3; /* XBS Control Register */
- u8 resv6[0xEC];
- u32 prs4; /* XBS Priority Register */
- u8 resv7[0xC];
- u32 crs4; /* XBS Control Register */
- u8 resv8[0xEC];
- u32 prs5; /* XBS Priority Register */
- u8 resv9[0xC];
- u32 crs5; /* XBS Control Register */
- u8 resv10[0xEC];
- u32 prs6; /* XBS Priority Register */
- u8 resv11[0xC];
- u32 crs6; /* XBS Control Register */
- u8 resv12[0xEC];
- u32 prs7; /* XBS Priority Register */
- u8 resv13[0xC];
- u32 crs7; /* XBS Control Register */
-} xbs_t;
-
-/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-
-typedef struct fbcs {
- u32 csar0; /* Chip-select Address Register */
- u32 csmr0; /* Chip-select Mask Register */
- u32 cscr0; /* Chip-select Control Register */
- u32 csar1; /* Chip-select Address Register */
- u32 csmr1; /* Chip-select Mask Register */
- u32 cscr1; /* Chip-select Control Register */
- u32 csar2; /* Chip-select Address Register */
- u32 csmr2; /* Chip-select Mask Register */
- u32 cscr2; /* Chip-select Control Register */
- u32 csar3; /* Chip-select Address Register */
- u32 csmr3; /* Chip-select Mask Register */
- u32 cscr3; /* Chip-select Control Register */
-} fbcs_t;
-
-/*********************************************************************
-* Enhanced DMA (EDMA)
-*********************************************************************/
-
-typedef struct edma {
- u32 cr;
- u32 es;
- u8 resv0[0x6];
- u16 erq;
- u8 resv1[0x6];
- u16 eei;
- u8 serq;
- u8 cerq;
- u8 seei;
- u8 ceei;
- u8 cint;
- u8 cerr;
- u8 ssrt;
- u8 cdne;
- u8 resv2[0x6];
- u16 intr;
- u8 resv3[0x6];
- u16 err;
- u8 resv4[0xD0];
- u8 dchpri0;
- u8 dchpri1;
- u8 dchpri2;
- u8 dchpri3;
- u8 dchpri4;
- u8 dchpri5;
- u8 dchpri6;
- u8 dchpri7;
- u8 dchpri8;
- u8 dchpri9;
- u8 dchpri10;
- u8 dchpri11;
- u8 dchpri12;
- u8 dchpri13;
- u8 dchpri14;
- u8 dchpri15;
- u8 resv5[0xEF0];
- u32 tcd0_saddr;
- u16 tcd0_attr;
- u16 tcd0_soff;
- u32 tcd0_nbytes;
- u32 tcd0_slast;
- u32 tcd0_daddr;
- union {
- u16 tcd0_citer_elink;
- u16 tcd0_citer;
- };
- u16 tcd0_doff;
- u32 tcd0_dlast_sga;
- union {
- u16 tcd0_biter_elink;
- u16 tcd0_biter;
- };
- u16 tcd0_csr;
- u32 tcd1_saddr;
- u16 tcd1_attr;
- u16 tcd1_soff;
- u32 tcd1_nbytes;
- u32 tcd1_slast;
- u32 tcd1_daddr;
- union {
- u16 tcd1_citer_elink;
- u16 tcd1_citer;
- };
- u16 tcd1_doff;
- u32 tcd1_dlast_sga;
- union {
- u16 tcd1_biter;
- u16 tcd1_biter_elink;
- };
- u16 tcd1_csr;
- u32 tcd2_saddr;
- u16 tcd2_attr;
- u16 tcd2_soff;
- u32 tcd2_nbytes;
- u32 tcd2_slast;
- u32 tcd2_daddr;
- union {
- u16 tcd2_citer;
- u16 tcd2_citer_elink;
- };
- u16 tcd2_doff;
- u32 tcd2_dlast_sga;
- union {
- u16 tcd2_biter_elink;
- u16 tcd2_biter;
- };
- u16 tcd2_csr;
- u32 tcd3_saddr;
- u16 tcd3_attr;
- u16 tcd3_soff;
- u32 tcd3_nbytes;
- u32 tcd3_slast;
- u32 tcd3_daddr;
- union {
- u16 tcd3_citer;
- u16 tcd3_citer_elink;
- };
- u16 tcd3_doff;
- u32 tcd3_dlast_sga;
- union {
- u16 tcd3_biter_elink;
- u16 tcd3_biter;
- };
- u16 tcd3_csr;
- u32 tcd4_saddr;
- u16 tcd4_attr;
- u16 tcd4_soff;
- u32 tcd4_nbytes;
- u32 tcd4_slast;
- u32 tcd4_daddr;
- union {
- u16 tcd4_citer;
- u16 tcd4_citer_elink;
- };
- u16 tcd4_doff;
- u32 tcd4_dlast_sga;
- union {
- u16 tcd4_biter;
- u16 tcd4_biter_elink;
- };
- u16 tcd4_csr;
- u32 tcd5_saddr;
- u16 tcd5_attr;
- u16 tcd5_soff;
- u32 tcd5_nbytes;
- u32 tcd5_slast;
- u32 tcd5_daddr;
- union {
- u16 tcd5_citer;
- u16 tcd5_citer_elink;
- };
- u16 tcd5_doff;
- u32 tcd5_dlast_sga;
- union {
- u16 tcd5_biter_elink;
- u16 tcd5_biter;
- };
- u16 tcd5_csr;
- u32 tcd6_saddr;
- u16 tcd6_attr;
- u16 tcd6_soff;
- u32 tcd6_nbytes;
- u32 tcd6_slast;
- u32 tcd6_daddr;
- union {
- u16 tcd6_citer;
- u16 tcd6_citer_elink;
- };
- u16 tcd6_doff;
- u32 tcd6_dlast_sga;
- union {
- u16 tcd6_biter_elink;
- u16 tcd6_biter;
- };
- u16 tcd6_csr;
- u32 tcd7_saddr;
- u16 tcd7_attr;
- u16 tcd7_soff;
- u32 tcd7_nbytes;
- u32 tcd7_slast;
- u32 tcd7_daddr;
- union {
- u16 tcd7_citer;
- u16 tcd7_citer_elink;
- };
- u16 tcd7_doff;
- u32 tcd7_dlast_sga;
- union {
- u16 tcd7_biter_elink;
- u16 tcd7_biter;
- };
- u16 tcd7_csr;
- u32 tcd8_saddr;
- u16 tcd8_attr;
- u16 tcd8_soff;
- u32 tcd8_nbytes;
- u32 tcd8_slast;
- u32 tcd8_daddr;
- union {
- u16 tcd8_citer;
- u16 tcd8_citer_elink;
- };
- u16 tcd8_doff;
- u32 tcd8_dlast_sga;
- union {
- u16 tcd8_biter_elink;
- u16 tcd8_biter;
- };
- u16 tcd8_csr;
- u32 tcd9_saddr;
- u16 tcd9_attr;
- u16 tcd9_soff;
- u32 tcd9_nbytes;
- u32 tcd9_slast;
- u32 tcd9_daddr;
- union {
- u16 tcd9_citer_elink;
- u16 tcd9_citer;
- };
- u16 tcd9_doff;
- u32 tcd9_dlast_sga;
- union {
- u16 tcd9_biter_elink;
- u16 tcd9_biter;
- };
- u16 tcd9_csr;
- u32 tcd10_saddr;
- u16 tcd10_attr;
- u16 tcd10_soff;
- u32 tcd10_nbytes;
- u32 tcd10_slast;
- u32 tcd10_daddr;
- union {
- u16 tcd10_citer_elink;
- u16 tcd10_citer;
- };
- u16 tcd10_doff;
- u32 tcd10_dlast_sga;
- union {
- u16 tcd10_biter;
- u16 tcd10_biter_elink;
- };
- u16 tcd10_csr;
- u32 tcd11_saddr;
- u16 tcd11_attr;
- u16 tcd11_soff;
- u32 tcd11_nbytes;
- u32 tcd11_slast;
- u32 tcd11_daddr;
- union {
- u16 tcd11_citer;
- u16 tcd11_citer_elink;
- };
- u16 tcd11_doff;
- u32 tcd11_dlast_sga;
- union {
- u16 tcd11_biter;
- u16 tcd11_biter_elink;
- };
- u16 tcd11_csr;
- u32 tcd12_saddr;
- u16 tcd12_attr;
- u16 tcd12_soff;
- u32 tcd12_nbytes;
- u32 tcd12_slast;
- u32 tcd12_daddr;
- union {
- u16 tcd12_citer;
- u16 tcd12_citer_elink;
- };
- u16 tcd12_doff;
- u32 tcd12_dlast_sga;
- union {
- u16 tcd12_biter;
- u16 tcd12_biter_elink;
- };
- u16 tcd12_csr;
- u32 tcd13_saddr;
- u16 tcd13_attr;
- u16 tcd13_soff;
- u32 tcd13_nbytes;
- u32 tcd13_slast;
- u32 tcd13_daddr;
- union {
- u16 tcd13_citer_elink;
- u16 tcd13_citer;
- };
- u16 tcd13_doff;
- u32 tcd13_dlast_sga;
- union {
- u16 tcd13_biter_elink;
- u16 tcd13_biter;
- };
- u16 tcd13_csr;
- u32 tcd14_saddr;
- u16 tcd14_attr;
- u16 tcd14_soff;
- u32 tcd14_nbytes;
- u32 tcd14_slast;
- u32 tcd14_daddr;
- union {
- u16 tcd14_citer;
- u16 tcd14_citer_elink;
- };
- u16 tcd14_doff;
- u32 tcd14_dlast_sga;
- union {
- u16 tcd14_biter_elink;
- u16 tcd14_biter;
- };
- u16 tcd14_csr;
- u32 tcd15_saddr;
- u16 tcd15_attr;
- u16 tcd15_soff;
- u32 tcd15_nbytes;
- u32 tcd15_slast;
- u32 tcd15_daddr;
- union {
- u16 tcd15_citer_elink;
- u16 tcd15_citer;
- };
- u16 tcd15_doff;
- u32 tcd15_dlast_sga;
- union {
- u16 tcd15_biter;
- u16 tcd15_biter_elink;
- };
- u16 tcd15_csr;
-} edma_t;
-
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
-
+/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
-/*********************************************************************
-* Global Interrupt Acknowledge (IACK)
-*********************************************************************/
-
+/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 gl7iack;
} iack_t;
-/*********************************************************************
-* DMA Serial Peripheral Interface (DSPI)
-*********************************************************************/
-
-typedef struct dspi {
- u32 dmcr;
- u8 resv0[0x4];
- u32 dtcr;
- u32 dctar0;
- u32 dctar1;
- u32 dctar2;
- u32 dctar3;
- u32 dctar4;
- u32 dctar5;
- u32 dctar6;
- u32 dctar7;
- u32 dsr;
- u32 dirsr;
- u32 dtfr;
- u32 drfr;
- u32 dtfdr0;
- u32 dtfdr1;
- u32 dtfdr2;
- u32 dtfdr3;
- u8 resv1[0x30];
- u32 drfdr0;
- u32 drfdr1;
- u32 drfdr2;
- u32 drfdr3;
-} dspi_t;
-
-/*********************************************************************
-* Edge Port Module (EPORT)
-*********************************************************************/
-
+/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epfr;
} eport_t;
-/*********************************************************************
-* Watchdog Timer Modules (WTM)
-*********************************************************************/
-
+/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
u16 wmr;
u16 wsr;
} wtm_t;
-/*********************************************************************
-* Serial Boot Facility (SBF)
-*********************************************************************/
-
+/* Serial Boot Facility (SBF) */
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
+/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
+/* Chip Configuration Module (CCM) */
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-
+/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
-/*********************************************************************
-* Random Number Generator (RNG)
-*********************************************************************/
-
+/* Random Number Generator (RNG) */
typedef struct rng {
u32 rngcr;
u32 rngsr;
u32 rngout;
} rng_t;
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
+/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
-typedef struct ssi {
- u32 tx0;
- u32 tx1;
- u32 rx0;
- u32 rx1;
- u32 cr;
- u32 isr;
- u32 ier;
- u32 tcr;
- u32 rcr;
- u32 ccr;
- u8 resv0[0x4];
- u32 fcsr;
- u8 resv1[0x8];
- u32 acr;
- u32 acadd;
- u32 acdat;
- u32 atag;
- u32 tmask;
- u32 rmask;
-} ssi_t;
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
+/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
-/********************************************************************/
+
+typedef struct scm2 {
+ u8 rsvd1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 */
+ u16 rsvd2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 */
+ u8 rsvd3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B */
+ u8 rsvd4[3]; /* 0x1C - 0x1E */
+ u8 scmisr; /* 0x1F */
+ u32 rsvd5; /* 0x20 - 0x23 */
+ u8 bcr; /* 0x24 */
+ u8 rsvd6[74]; /* 0x25 - 0x6F */
+ u32 cfadr; /* 0x70 */
+ u8 rsvd7; /* 0x74 */
+ u8 cfier; /* 0x75 */
+ u8 cfloc; /* 0x76 */
+ u8 cfatr; /* 0x77 */
+ u32 rsvd8; /* 0x78 - 0x7B */
+ u32 cfdtr; /* 0x7C */
+} scm2_t;
typedef struct rtcex {
u32 rsvd1[3];
#ifndef __MCF5445X__
#define __MCF5445X__
-/*********************************************************************
-* Cross-bar switch (XBS)
-*********************************************************************/
-
-/* Bit definitions and macros for PRS group */
-#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
-#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
-#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
-#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
-#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
-#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
-#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
-
-/* Bit definitions and macros for CRS group */
-#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
-#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
-#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
-#define XBS_CRS_RO (0x80000000) /* Read Only */
-
-#define XBS_CRS_PCTL_PARK_FIELD (0)
-#define XBS_CRS_PCTL_PARK_ON_LAST (1)
-#define XBS_CRS_PCTL_PARK_NONE (2)
-#define XBS_CRS_PCTL_PARK_CORE (0)
-#define XBS_CRS_PCTL_PARK_EDMA (1)
-#define XBS_CRS_PCTL_PARK_FEC0 (2)
-#define XBS_CRS_PCTL_PARK_FEC1 (3)
-#define XBS_CRS_PCTL_PARK_PCI (5)
-#define XBS_CRS_PCTL_PARK_USB (6)
-#define XBS_CRS_PCTL_PARK_SBF (7)
-
-/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-
-/* Bit definitions and macros for CSAR group */
-#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
-
-/* Bit definitions and macros for CSMR group */
-#define FBCS_CSMR_V (0x00000001) /* Valid bit */
-#define FBCS_CSMR_WP (0x00000100) /* Write protect */
-#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
-#define FBCS_CSMR_BAM_4G (0xFFFF0000)
-#define FBCS_CSMR_BAM_2G (0x7FFF0000)
-#define FBCS_CSMR_BAM_1G (0x3FFF0000)
-#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
-#define FBCS_CSMR_BAM_512M (0x1FFF0000)
-#define FBCS_CSMR_BAM_256M (0x0FFF0000)
-#define FBCS_CSMR_BAM_128M (0x07FF0000)
-#define FBCS_CSMR_BAM_64M (0x03FF0000)
-#define FBCS_CSMR_BAM_32M (0x01FF0000)
-#define FBCS_CSMR_BAM_16M (0x00FF0000)
-#define FBCS_CSMR_BAM_8M (0x007F0000)
-#define FBCS_CSMR_BAM_4M (0x003F0000)
-#define FBCS_CSMR_BAM_2M (0x001F0000)
-#define FBCS_CSMR_BAM_1M (0x000F0000)
-#define FBCS_CSMR_BAM_1024K (0x000F0000)
-#define FBCS_CSMR_BAM_512K (0x00070000)
-#define FBCS_CSMR_BAM_256K (0x00030000)
-#define FBCS_CSMR_BAM_128K (0x00010000)
-#define FBCS_CSMR_BAM_64K (0x00000000)
-
-/* Bit definitions and macros for CSCR group */
-#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
-#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
-#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
-#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
-#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
-#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
-#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
-#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
-#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
-#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
-#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
-
-#define FBCS_CSCR_PS_8 (0x00000040)
-#define FBCS_CSCR_PS_16 (0x00000080)
-#define FBCS_CSCR_PS_32 (0x00000000)
-
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
-/*********************************************************************
-* DMA Serial Peripheral Interface (DSPI)
-*********************************************************************/
-
-/* Bit definitions and macros for DMCR */
-#define DSPI_DMCR_HALT (0x00000001)
-#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
-#define DSPI_DMCR_CRXF (0x00000400)
-#define DSPI_DMCR_CTXF (0x00000800)
-#define DSPI_DMCR_DRXF (0x00001000)
-#define DSPI_DMCR_DTXF (0x00002000)
-#define DSPI_DMCR_CSIS0 (0x00010000)
-#define DSPI_DMCR_CSIS2 (0x00040000)
-#define DSPI_DMCR_CSIS3 (0x00080000)
-#define DSPI_DMCR_CSIS5 (0x00200000)
-#define DSPI_DMCR_ROOE (0x01000000)
-#define DSPI_DMCR_PCSSE (0x02000000)
-#define DSPI_DMCR_MTFE (0x04000000)
-#define DSPI_DMCR_FRZ (0x08000000)
-#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
-#define DSPI_DMCR_CSCK (0x40000000)
-#define DSPI_DMCR_MSTR (0x80000000)
-
-/* Bit definitions and macros for DTCR */
-#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for DCTAR group */
-#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
-#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
-#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
-#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
-#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
-#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
-#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
-#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
-#define DSPI_DCTAR_LSBFE (0x01000000)
-#define DSPI_DCTAR_CPHA (0x02000000)
-#define DSPI_DCTAR_CPOL (0x04000000)
-#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
-#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
-#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
-#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
-#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
-#define DSPI_DCTAR_PASC_1CLK (0x00000000)
-#define DSPI_DCTAR_PASC_3CLK (0x00100000)
-#define DSPI_DCTAR_PASC_5CLK (0x00200000)
-#define DSPI_DCTAR_PASC_7CLK (0x00300000)
-#define DSPI_DCTAR_PDT_1CLK (0x00000000)
-#define DSPI_DCTAR_PDT_3CLK (0x00040000)
-#define DSPI_DCTAR_PDT_5CLK (0x00080000)
-#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
-#define DSPI_DCTAR_PBR_1CLK (0x00000000)
-#define DSPI_DCTAR_PBR_3CLK (0x00010000)
-#define DSPI_DCTAR_PBR_5CLK (0x00020000)
-#define DSPI_DCTAR_PBR_7CLK (0x00030000)
-
-/* Bit definitions and macros for DSR */
-#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
-#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
-#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
-#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
-#define DSPI_DSR_RFDF (0x00020000)
-#define DSPI_DSR_RFOF (0x00080000)
-#define DSPI_DSR_TFFF (0x02000000)
-#define DSPI_DSR_TFUF (0x08000000)
-#define DSPI_DSR_EOQF (0x10000000)
-#define DSPI_DSR_TXRXS (0x40000000)
-#define DSPI_DSR_TCF (0x80000000)
-
-/* Bit definitions and macros for DIRSR */
-#define DSPI_DIRSR_RFDFS (0x00010000)
-#define DSPI_DIRSR_RFDFE (0x00020000)
-#define DSPI_DIRSR_RFOFE (0x00080000)
-#define DSPI_DIRSR_TFFFS (0x01000000)
-#define DSPI_DIRSR_TFFFE (0x02000000)
-#define DSPI_DIRSR_TFUFE (0x08000000)
-#define DSPI_DIRSR_EOQFE (0x10000000)
-#define DSPI_DIRSR_TCFE (0x80000000)
-
-/* Bit definitions and macros for DTFR */
-#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
-#define DSPI_DTFR_CS0 (0x00010000)
-#define DSPI_DTFR_CS2 (0x00040000)
-#define DSPI_DTFR_CS3 (0x00080000)
-#define DSPI_DTFR_CS5 (0x00200000)
-#define DSPI_DTFR_CTCNT (0x04000000)
-#define DSPI_DTFR_EOQ (0x08000000)
-#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
-#define DSPI_DTFR_CONT (0x80000000)
-
-/* Bit definitions and macros for DRFR */
-#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
-
-/* Bit definitions and macros for DTFDR group */
-#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
-#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for DRFDR group */
-#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
-
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
-/* Bit definitions and macros for CR */
-#define SSI_CR_SSI_EN (0x00000001)
-#define SSI_CR_TE (0x00000002)
-#define SSI_CR_RE (0x00000004)
-#define SSI_CR_NET (0x00000008)
-#define SSI_CR_SYN (0x00000010)
-#define SSI_CR_I2S(x) (((x)&0x00000003)<<5)
-#define SSI_CR_MCE (0x00000080)
-#define SSI_CR_TCH (0x00000100)
-#define SSI_CR_CIS (0x00000200)
-#define SSI_CR_I2S_NORMAL (0x00000000)
-#define SSI_CR_I2S_MASTER (0x00000020)
-#define SSI_CR_I2S_SLAVE (0x00000040)
-
-/* Bit definitions and macros for ISR */
-#define SSI_ISR_TFE0 (0x00000001)
-#define SSI_ISR_TFE1 (0x00000002)
-#define SSI_ISR_RFF0 (0x00000004)
-#define SSI_ISR_RFF1 (0x00000008)
-#define SSI_ISR_RLS (0x00000010)
-#define SSI_ISR_TLS (0x00000020)
-#define SSI_ISR_RFS (0x00000040)
-#define SSI_ISR_TFS (0x00000080)
-#define SSI_ISR_TUE0 (0x00000100)
-#define SSI_ISR_TUE1 (0x00000200)
-#define SSI_ISR_ROE0 (0x00000400)
-#define SSI_ISR_ROE1 (0x00000800)
-#define SSI_ISR_TDE0 (0x00001000)
-#define SSI_ISR_TDE1 (0x00002000)
-#define SSI_ISR_RDR0 (0x00004000)
-#define SSI_ISR_RDR1 (0x00008000)
-#define SSI_ISR_RXT (0x00010000)
-#define SSI_ISR_CMDDU (0x00020000)
-#define SSI_ISR_CMDAU (0x00040000)
-
-/* Bit definitions and macros for IER */
-#define SSI_IER_TFE0 (0x00000001)
-#define SSI_IER_TFE1 (0x00000002)
-#define SSI_IER_RFF0 (0x00000004)
-#define SSI_IER_RFF1 (0x00000008)
-#define SSI_IER_RLS (0x00000010)
-#define SSI_IER_TLS (0x00000020)
-#define SSI_IER_RFS (0x00000040)
-#define SSI_IER_TFS (0x00000080)
-#define SSI_IER_TUE0 (0x00000100)
-#define SSI_IER_TUE1 (0x00000200)
-#define SSI_IER_ROE0 (0x00000400)
-#define SSI_IER_ROE1 (0x00000800)
-#define SSI_IER_TDE0 (0x00001000)
-#define SSI_IER_TDE1 (0x00002000)
-#define SSI_IER_RDR0 (0x00004000)
-#define SSI_IER_RDR1 (0x00008000)
-#define SSI_IER_RXT (0x00010000)
-#define SSI_IER_CMDU (0x00020000)
-#define SSI_IER_CMDAU (0x00040000)
-#define SSI_IER_TIE (0x00080000)
-#define SSI_IER_TDMAE (0x00100000)
-#define SSI_IER_RIE (0x00200000)
-#define SSI_IER_RDMAE (0x00400000)
-
-/* Bit definitions and macros for TCR */
-#define SSI_TCR_TEFS (0x00000001)
-#define SSI_TCR_TFSL (0x00000002)
-#define SSI_TCR_TFSI (0x00000004)
-#define SSI_TCR_TSCKP (0x00000008)
-#define SSI_TCR_TSHFD (0x00000010)
-#define SSI_TCR_TXDIR (0x00000020)
-#define SSI_TCR_TFDIR (0x00000040)
-#define SSI_TCR_TFEN0 (0x00000080)
-#define SSI_TCR_TFEN1 (0x00000100)
-#define SSI_TCR_TXBIT0 (0x00000200)
-
-/* Bit definitions and macros for RCR */
-#define SSI_RCR_REFS (0x00000001)
-#define SSI_RCR_RFSL (0x00000002)
-#define SSI_RCR_RFSI (0x00000004)
-#define SSI_RCR_RSCKP (0x00000008)
-#define SSI_RCR_RSHFD (0x00000010)
-#define SSI_RCR_RFEN0 (0x00000080)
-#define SSI_RCR_RFEN1 (0x00000100)
-#define SSI_RCR_RXBIT0 (0x00000200)
-#define SSI_RCR_RXEXT (0x00000400)
-
-/* Bit definitions and macros for CCR */
-#define SSI_CCR_PM(x) (((x)&0x000000FF))
-#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
-#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
-#define SSI_CCR_PSR (0x00020000)
-#define SSI_CCR_DIV2 (0x00040000)
-
-/* Bit definitions and macros for FCSR */
-#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
-#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
-#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
-#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
-#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
-#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
-#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
-#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
-
-/* Bit definitions and macros for ACR */
-#define SSI_ACR_AC97EN (0x00000001)
-#define SSI_ACR_FV (0x00000002)
-#define SSI_ACR_TIF (0x00000004)
-#define SSI_ACR_RD (0x00000008)
-#define SSI_ACR_WR (0x00000010)
-#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
-
-/* Bit definitions and macros for ACADD */
-#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
-
-/* Bit definitions and macros for ACDAT */
-#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
-
-/* Bit definitions and macros for ATAG */
-#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
-
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
-
-#define PCI_IDR_DEVID (
+#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
/********************************************************************/
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