mpc85xx: Adding more registers and options

This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.

Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index e46dcb70475e4a37bf50c83b93a4ff8ea7729962..4e768d39ba6371e5ae0a1ff36b940a4702c33d1e 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/processor.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -79,6 +80,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+       out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+       out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       out_be32(&ddr->err_disable, regs->err_disable);
+       out_be32(&ddr->err_int_en, regs->err_int_en);
+       for (i = 0; i < 32; i++)
+               out_be32(&ddr->debug[i], regs->debug[i]);
 
        /* Set, but do not enable the memory */
        temp_sdram_cfg = regs->ddr_sdram_cfg;
@@ -93,8 +100,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
            && in_be32(&ddr->sdram_cfg) & 0x80000) {
                /* set DEBUG_1[31] */
-               u32 temp = in_be32(&ddr->debug_1);
-               out_be32(&ddr->debug_1, temp | 1);
+               setbits_be32(&ddr->debug[0], 1);
        }
 #endif
 

diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 3de2113bdad449d5f4ef0f87b1835e02cc7a3c26..04aeb40753e39572a0f953a24306840ad1c9ee75 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -120,6 +120,11 @@ typedef struct fsl_ddr_cfg_regs_s {
        unsigned int ddr_sdram_rcw_1;
        unsigned int ddr_sdram_rcw_2;
        unsigned int ddr_eor;
+       unsigned int ddr_cdr1;
+       unsigned int ddr_cdr2;
+       unsigned int err_disable;
+       unsigned int err_int_en;
+       unsigned int debug[32];
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
@@ -175,6 +180,7 @@ typedef struct memctl_options_s {
        /* mirrior DIMMs for DDR3 */
        unsigned int mirrored_dimm;
        unsigned int quad_rank_present;
+       unsigned int ap_en;     /* address parity enable for RDIMM */
 
        /* Global Timing Parameters */
        unsigned int cas_latency_override;
@@ -210,6 +216,12 @@ typedef struct memctl_options_s {
        unsigned int zq_en;
        /* Write leveling */
        unsigned int wrlvl_en;
+       /* RCW override for RDIMM */
+       unsigned int rcw_override;
+       unsigned int rcw_1;
+       unsigned int rcw_2;
+       /* control register 1 */
+       unsigned int ddr_cdr1;
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 93a9e6ceca4d29b147c95434a838ae55664f9767..6bd83ba166137f385fa6de3528750b44bbfdac0f 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -222,25 +222,8 @@ typedef struct ccsr_ddr {
        u32     capture_ext_address;    /* Error Extended Addr Capture */
        u32     err_sbe;                /* Single-Bit ECC Error Management */
        u8      res11[164];
-       u32     debug_1;
-       u32     debug_2;
-       u32     debug_3;
-       u32     debug_4;
-       u32     debug_5;
-       u32     debug_6;
-       u32     debug_7;
-       u32     debug_8;
-       u32     debug_9;
-       u32     debug_10;
-       u32     debug_11;
-       u32     debug_12;
-       u32     debug_13;
-       u32     debug_14;
-       u32     debug_15;
-       u32     debug_16;
-       u32     debug_17;
-       u32     debug_18;
-       u8      res12[184];
+       u32     debug[32];              /* debug_1 to debug_32 */
+       u8      res12[128];
 } ccsr_ddr_t;
 
 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */

diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index b2d3185351605989dfcf06996457d8e30771eecc..39a9e2131a97b131dcecbfb081ed6627795d4a16 100644 (file)
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -240,7 +240,7 @@ static phys_size_t sdram_setup(int casl)
         * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
         *    training
         */
-       ddr->debug_3 |= 0x00000400;
+       ddr->debug[2] |= 0x00000400;
 
        /*
         * 5. Wait 200 micro-seconds
@@ -282,18 +282,18 @@ static phys_size_t sdram_setup(int casl)
        /*
         * 8. Clear D3[21] to re-enable data training
         */
-       ddr->debug_3 &= ~0x00000400;
+       ddr->debug[2] &= ~0x00000400;
 
        /*
         * 9. Set D2(21) to force data training to run
         */
-       ddr->debug_2 |= 0x00000400;
+       ddr->debug[1] |= 0x00000400;
 
        /*
         * 10. Poll on D2[21] until it is cleared by hardware
         */
        asm ("sync;isync;msync");
-       while (ddr->debug_2 & 0x00000400)
+       while (ddr->debug[1] & 0x00000400)
                asm ("eieio");
 
        /*