sh: 7724: Remove CPU support

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>

diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index b558d6935cc72e00c22894c093c967ea7641a834..977b648dd49c64d5a9106d674842718096e61eb6 100644 (file)
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -30,8 +30,6 @@
 # include <asm/cpu_sh7722.h>
 #elif defined (CONFIG_CPU_SH7723)
 # include <asm/cpu_sh7723.h>
-#elif defined (CONFIG_CPU_SH7724)
-# include <asm/cpu_sh7724.h>
 #elif defined (CONFIG_CPU_SH7734)
 # include <asm/cpu_sh7734.h>
 #elif defined (CONFIG_CPU_SH7752)

diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
deleted file mode 100644 (file)
index 7b21795..0000000
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2011 Renesas Solutions Corp.
- *
- * SH7724 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7724_H_
-#define _ASM_CPU_SH7724_H_
-
-#define CACHE_OC_NUM_WAYS      4
-#define CCR_CACHE_INIT 0x0000090d
-
-/* EXP */
-#define TRA            0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-
-/* MMU */
-#define PTEH   0xFF000000
-#define PTEL   0xFF000004
-#define TTB            0xFF000008
-#define TEA            0xFF00000C
-#define MMUCR  0xFF000010
-#define PASCR  0xFF000070
-#define IRMCR  0xFF000078
-
-/* CACHE */
-#define CCR            0xFF00001C
-#define RAMCR  0xFF000074
-
-/* INTC */
-
-/* BSC */
-#define MMSELR         0xFF800020
-#define CMNCR          0xFEC10000
-#define        CS0BCR          0xFEC10004
-#define CS2BCR         0xFEC10008
-#define CS4BCR         0xFEC10010
-#define CS5ABCR                0xFEC10014
-#define CS5BBCR                0xFEC10018
-#define CS6ABCR                0xFEC1001C
-#define CS6BBCR                0xFEC10020
-#define CS0WCR         0xFEC10024
-#define CS2WCR         0xFEC10028
-#define CS4WCR         0xFEC10030
-#define CS5AWCR                0xFEC10034
-#define CS5BWCR                0xFEC10038
-#define CS6AWCR                0xFEC1003C
-#define CS6BWCR                0xFEC10040
-#define RBWTCNT                0xFEC10054
-
-/* SBSC */
-#define SBSC_SDCR      0xFE400008
-#define SBSC_SDWCR     0xFE40000C
-#define SBSC_SDPCR     0xFE400010
-#define SBSC_RTCSR     0xFE400014
-#define SBSC_RTCNT     0xFE400018
-#define SBSC_RTCOR     0xFE40001C
-#define SBSC_RFCR      0xFE400020
-
-/* DSBC */
-#define DBKIND         0xFD000008
-#define DBSTATE                0xFD00000C
-#define DBEN           0xFD000010
-#define DBCMDCNT       0xFD000014
-#define DBCKECNT       0xFD000018
-#define DBCONF         0xFD000020
-#define DBTR0          0xFD000030
-#define DBTR1          0xFD000034
-#define DBTR2          0xFD000038
-#define DBTR3          0xFD00003C
-#define DBRFPDN0       0xFD000040
-#define DBRFPDN1       0xFD000044
-#define DBRFPDN2       0xFD000048
-#define DBRFSTS                0xFD00004C
-#define DBMRCNT                0xFD000060
-#define DBPDCNT0       0xFD000108
-
-/* DMAC */
-
-/* CPG */
-#define FRQCRA         0xA4150000
-#define FRQCRB         0xA4150004
-#define FRQCR          FRQCRA
-#define VCLKCR      0xA4150004
-#define SCLKACR     0xA4150008
-#define SCLKBCR     0xA415000C
-#define IRDACLKCR   0xA4150018
-#define PLLCR       0xA4150024
-#define DLLFRQ      0xA4150050
-
-/* LOW POWER MODE */
-#define STBCR       0xA4150020
-#define MSTPCR0     0xA4150030
-#define MSTPCR1     0xA4150034
-#define MSTPCR2     0xA4150038
-
-/* RWDT */
-#define RWTCNT      0xA4520000
-#define RWTCSR      0xA4520004
-#define WTCNT          RWTCNT
-
-/* TMU */
-#define TMU_BASE       0xFFD80000
-
-/* TPU */
-
-/* CMT */
-#define CMSTR       0xA44A0000
-#define CMCSR       0xA44A0060
-#define CMCNT       0xA44A0064
-#define CMCOR       0xA44A0068
-
-/* MSIOF */
-
-/* SCIF */
-#define SCIF0_BASE  0xFFE00000
-#define SCIF1_BASE  0xFFE10000
-#define SCIF2_BASE  0xFFE20000
-#define SCIF3_BASE  0xa4e30000
-#define SCIF4_BASE  0xa4e40000
-#define SCIF5_BASE  0xa4e50000
-
-/* RTC */
-/* IrDA */
-/* KEYSC */
-/* USB */
-/* IIC */
-/* FLCTL */
-/* VPU */
-/* VIO(CEU) */
-/* VIO(VEU) */
-/* VIO(BEU) */
-/* 2DG */
-/* LCDC */
-/* VOU */
-/* TSIF */
-/* SIU */
-/* ATAPI */
-
-/* PFC */
-#define PACR        0xA4050100
-#define PBCR        0xA4050102
-#define PCCR        0xA4050104
-#define PDCR        0xA4050106
-#define PECR        0xA4050108
-#define PFCR        0xA405010A
-#define PGCR        0xA405010C
-#define PHCR        0xA405010E
-#define PJCR        0xA4050110
-#define PKCR        0xA4050112
-#define PLCR        0xA4050114
-#define PMCR        0xA4050116
-#define PNCR        0xA4050118
-#define PQCR        0xA405011A
-#define PRCR        0xA405011C
-#define PSCR        0xA405011E
-#define PTCR        0xA4050140
-#define PUCR        0xA4050142
-#define PVCR        0xA4050144
-#define PWCR        0xA4050146
-#define PXCR        0xA4050148
-#define PYCR        0xA405014A
-#define PZCR        0xA405014C
-#define PSELA       0xA405014E
-#define PSELB       0xA4050150
-#define PSELC       0xA4050152
-#define PSELD       0xA4050154
-#define PSELE       0xA4050156
-#define HIZCRA      0xA4050158
-#define HIZCRB      0xA405015A
-#define HIZCRC      0xA405015C
-#define HIZCRD      0xA405015E
-#define MSELCRA     0xA4050180
-#define MSELCRB     0xA4050182
-#define PULCR       0xA4050184
-#define DRVCRA      0xA405018A
-#define DRVCRB      0xA405018C
-
-/* I/O Port */
-#define PADR        0xA4050120
-#define PBDR        0xA4050122
-#define PCDR        0xA4050124
-#define PDDR        0xA4050126
-#define PEDR        0xA4050128
-#define PFDR        0xA405012A
-#define PGDR        0xA405012C
-#define PHDR        0xA405012E
-#define PJDR        0xA4050130
-#define PKDR        0xA4050132
-#define PLDR        0xA4050134
-#define PMDR        0xA4050136
-#define PNDR        0xA4050138
-#define PQDR        0xA405013A
-#define PRDR        0xA405013C
-#define PSDR        0xA405013E
-#define PTDR        0xA4050160
-#define PUDR        0xA4050162
-#define PVDR        0xA4050164
-#define PWDR        0xA4050166
-#define PXDR        0xA4050168
-#define PYDR        0xA405016A
-#define PZDR        0xA405016C
-
-/* UBC */
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7724_H_ */

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 4646f2ba4ec4ae213109f5cd588f2b1a408840ea..a2577e1e8ff1aaacceed1496123c7906acd17a35 100644 (file)
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -425,7 +425,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
                sh_eth_write(port_info, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
                sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2)
                val = ECMR_RTM;
 #endif
        } else if (phy->speed == 10) {

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index cd8190062a6b195eb5c65e94eb44bb7d17a2eb5a..d8b4bda3ef9c339cb081e5d250494b30136de2b2 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -295,9 +295,6 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR   0xfef00000
 #endif
-#elif defined(CONFIG_CPU_SH7724)
-#define SH_ETH_TYPE_ETHER
-#define BASE_IO_ADDR   0xA4600000
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xE9A00000

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index deb4b647c6f0a9a5352dd5e5b248801461de26a9..c6f4778628b7169984835ad79afdef8abf548dff 100644 (file)
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -107,11 +107,6 @@ struct uart_port {
 # define SCSPTR5                0xa4050128
 # define SCIF_ORER              0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7724)
-# define SCIF_ORER              0x0001  /* overrun error bit */
-# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
-       0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
-       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
 #elif defined(CONFIG_CPU_SH7734)
 # define SCSPTR0 0xFFE40020
 # define SCSPTR1 0xFFE41020
@@ -256,8 +251,6 @@ struct uart_port {
        defined(CONFIG_CPU_SH7786)  || \
        defined(CONFIG_CPU_SHX3)
 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
-#elif defined(CONFIG_CPU_SH7724)
-#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
 #else
 #define SCI_CTRL_FLAGS_REIE 0
 #endif
@@ -494,7 +487,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
                                        sh4_scif_offset, sh4_scif_size) \
        CPU_SCIF_FNS(name)
-#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
                #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
                                        sh4_scif_offset, sh4_scif_size) \
                        CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
@@ -549,8 +542,7 @@ SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
 SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
 SCIF_FNS(DL,    0x00,  0) /* dummy */
-#elif defined(CONFIG_CPU_SH7723) ||\
-       defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
@@ -747,8 +739,7 @@ static inline int sci_rxd_in(struct uart_port *port)
        defined(CONFIG_SH73A0) || \
        defined(CONFIG_R8A7740)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SH7723) ||\
-       defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 {
        if (port->type == PORT_SCIF)

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 87c26df6d77924d8902a451057b0ad88ab80eee8..ba8493f7c3d913a7f4734af635e6f4ced099f309 100644 (file)
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -277,7 +277,6 @@ CONFIG_CPU_SH7706
 CONFIG_CPU_SH7720
 CONFIG_CPU_SH7722
 CONFIG_CPU_SH7723
-CONFIG_CPU_SH7724
 CONFIG_CPU_SH7734
 CONFIG_CPU_SH7750
 CONFIG_CPU_SH7751