mx31: define pins and init for UART2 and CSPI3

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c
index 1e7d48f8fb440928d0d6ec24e7a936676e826c81..b42dac3fbedc35c1767ac9b676efdcaec81a5374 100644 (file)
--- a/arch/arm/cpu/arm1136/mx31/devices.c
+++ b/arch/arm/cpu/arm1136/mx31/devices.c
@@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_MX31_UART2
+void mx31_uart2_hw_init(void)
+{
+       /* setup pins for UART2 */
+       mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
+       mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
+       mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
+       mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
+}
+#endif
+
 #ifdef CONFIG_MXC_SPI
+/*
+ * Note: putting several spi setups here makes no sense as they may differ
+ * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
+ */
 void mx31_spi2_hw_init(void)
 {
        /* SPI2 */

diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index 3e22d9a9975db034ffd704f56a574db5ca08e5ce..253a0e158481ef6338aa4c3d8472e0ce19b28959 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -40,6 +40,7 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config);
 extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
 
 void mx31_uart1_hw_init(void);
+void mx31_uart2_hw_init(void);
 void mx31_spi2_hw_init(void);
 void mxc_hw_watchdog_enable(void);
 void mxc_hw_watchdog_reset(void);

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6ce008d6d1ab51ba25a00350a3d057d81bc255b3..f487975e37e6d59ed4d91dc7b8df288d489df065 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -680,12 +680,23 @@ struct mx31_weim {
 
 /* Register offsets based on IOMUXC_BASE */
 /* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO             0x0c
+#define MUX_CTL_CSPI3_SCLK             0x0d
+#define MUX_CTL_CSPI3_SPI_RDY  0x0e
+#define MUX_CTL_CSPI3_MOSI             0x13
+
 #define MUX_CTL_USBH2_DATA1    0x40
 #define MUX_CTL_USBH2_DIR      0x44
 #define MUX_CTL_USBH2_STP      0x45
 #define MUX_CTL_USBH2_NXT      0x46
 #define MUX_CTL_USBH2_DATA0    0x47
 #define MUX_CTL_USBH2_CLK      0x4B
+
+#define MUX_CTL_TXD2           0x70
+#define MUX_CTL_RTS2           0x71
+#define MUX_CTL_CTS2           0x72
+#define MUX_CTL_RXD2           0x77
+
 #define MUX_CTL_RTS1           0x7c
 #define MUX_CTL_CTS1           0x7d
 #define MUX_CTL_DTR_DCE1       0x7e
@@ -743,6 +754,11 @@ struct mx31_weim {
 #define MUX_RTS1__UART1_RTS_B  IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
 #define MUX_CTS1__UART1_CTS_B  IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
 
+#define MUX_RXD2__UART2_RXD_MUX        IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX        IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B  IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B  IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)