Empirically set cpo and clk_adjust for mpc85xx DDR2 support

This patch is against u-boot-mpc85xx.git of www.denx.com

Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.

Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 679f3608f72e40c4766f022bf1822ae27303f7be..5dc223a53e3ff3d82ea55a841c0b8eaceed1acf5 100644 (file)
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -692,13 +692,10 @@ spd_sdram(void)
         */
        cpo = 0;
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
-               if (effective_data_rate == 266 || effective_data_rate == 333) {
+               if (effective_data_rate <= 333) {
                        cpo = 0x7;              /* READ_LAT + 5/4 */
-               } else if (effective_data_rate == 400) {
-                       cpo = 0x9;              /* READ_LAT + 7/4 */
                } else {
-                       /* Pure speculation */
-                       cpo = 0xb;
+                       cpo = 0x9;              /* READ_LAT + 7/4 */
                }
        }
 
@@ -905,7 +902,12 @@ spd_sdram(void)
        if (spd.mem_type == SPD_MEMTYPE_DDR)
                clk_adjust = 0x6;
        else
+#ifdef CONFIG_MPC8568
+               /* Empirally setting clk_adjust */
+               clk_adjust = 0x6;
+#else
                clk_adjust = 0x7;
+#endif
 
        ddr->sdram_clk_cntl = (0
                               | 0x80000000