]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: dts: ls1028a: disable the PCIe controller by default
authorMichael Walle <michael@walle.cc>
Wed, 13 Oct 2021 16:14:25 +0000 (18:14 +0200)
committerPriyanka Jain <priyanka.jain@nxp.com>
Tue, 9 Nov 2021 11:48:23 +0000 (17:18 +0530)
Disable the PCIe controllers by default, just like in the linux device
tree. But there is one catch, for linux they are enabled in-place by the
bootloader. Obviously, this doesn't work for the bootloader. Thus we
explicitly enable the controllers in the -u-boot.dtsi files.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
arch/arm/dts/fsl-ls1028a-qds.dtsi
arch/arm/dts/fsl-ls1028a-rdb.dts
arch/arm/dts/fsl-ls1028a.dtsi

index 68a3e0b7aa8f4e64cc94b9ccb717c59bb8ecd6df..37382e09f1eddd305d0de90c4fc08f3cdb3d47ad 100644 (file)
        u-boot,dm-pre-reloc;
 };
 
+/*
+ * u-boot will enable the device in the linux device tree in place. Because
+ * we are using the linux device tree, we have to enable the PCI controller
+ * ourselves.
+ */
+&pcie1 {
+       status = "okay";
+};
+
+&pcie2 {
+       status = "okay";
+};
+
 &soc {
        u-boot,dm-pre-reloc;
 };
index babd8445eebbe967eb5af0938600a19420529eec..0da0a7bc5db859e4c43ef21b635ef3935cc74008 100644 (file)
        status = "okay";
 };
 
+&pcie1 {
+       status = "okay";
+};
+
+&pcie2 {
+       status = "okay";
+};
+
 &usb0 {
        status = "okay";
 };
index 18ee363d75ba6e0ffaff5eb4c7f72c458bf7d890..537ebbc697cbc10c9946c76be1ba69653c485c92 100644 (file)
        status = "okay";
 };
 
+&pcie1 {
+       status = "okay";
+};
+
+&pcie2 {
+       status = "okay";
+};
+
 &usb0 {
        status = "okay";
 };
index f11e75032b8ebf768c8945621818636f53b8449f..d2f558d20818821b97d4d5eb275b57a7980f0b52 100644 (file)
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
                                  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                       status = "disabled";
                };
 
                pcie2: pcie@3500000 {
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */
                                  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                       status = "disabled";
                };
 
                cluster1_core0_watchdog: wdt@c000000 {