]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
clk: sifive: Factor-out PLL library as separate module
authorAnup Patel <Anup.Patel@wdc.com>
Tue, 25 Jun 2019 06:31:02 +0000 (06:31 +0000)
committerAndes <uboot@andestech.com>
Fri, 19 Jul 2019 06:24:51 +0000 (14:24 +0800)
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
drivers/clk/Kconfig
drivers/clk/Makefile
drivers/clk/analogbits/Kconfig [new file with mode: 0644]
drivers/clk/analogbits/Makefile [new file with mode: 0644]
drivers/clk/analogbits/wrpll-cln28hpc.c [moved from drivers/clk/sifive/wrpll-cln28hpc.c with 99% similarity]
drivers/clk/sifive/Kconfig
drivers/clk/sifive/Makefile
drivers/clk/sifive/fu540-prci.c
include/linux/clk/analogbits-wrpll-cln28hpc.h [moved from drivers/clk/sifive/analogbits-wrpll-cln28hpc.h with 100% similarity]

index 96969b9e30eca5dbc95ef566519354182baf8858..7b81eacf50e66a622d93084be27c80a235b44d5c 100644 (file)
@@ -98,6 +98,7 @@ config CLK_STM32MP1
          Enable the STM32 clock (RCC) driver. Enable support for
          manipulating STM32MP1's on-SoC clocks.
 
+source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/imx/Kconfig"
index 719b9b8e024334d4b60bae29c1c8aa6682834130..f0ced49e5a3b6287124180270a2f789e06e30178 100644 (file)
@@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 
+obj-y += analogbits/
 obj-y += imx/
 obj-y += tegra/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
diff --git a/drivers/clk/analogbits/Kconfig b/drivers/clk/analogbits/Kconfig
new file mode 100644 (file)
index 0000000..1d25e6f
--- /dev/null
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+       bool
diff --git a/drivers/clk/analogbits/Makefile b/drivers/clk/analogbits/Makefile
new file mode 100644 (file)
index 0000000..ec1bb40
--- /dev/null
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)    += wrpll-cln28hpc.o
similarity index 99%
rename from drivers/clk/sifive/wrpll-cln28hpc.c
rename to drivers/clk/analogbits/wrpll-cln28hpc.c
index d3778496935f1b77bba39195dbeb9ca33810a563..68eb1148b913fddd9005ae111d4cfdfa90513a58 100644 (file)
@@ -35,8 +35,7 @@
 #include <linux/err.h>
 #include <linux/log2.h>
 #include <linux/math64.h>
-
-#include "analogbits-wrpll-cln28hpc.h"
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
 
 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
 #define MIN_INPUT_FREQ                 7000000
index 644881b948755f86f47b8d0d33b7fdb21d43a54f..d90be1943fb48218bc5ee56a7c911dc8b6bf5e6a 100644 (file)
@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
-config CLK_ANALOGBITS_WRPLL_CLN28HPC
-       bool
-
 config CLK_SIFIVE
        bool "SiFive SoC driver support"
        depends on CLK
index f8263e79b70fdd466d1f5a850da95722f3d57248..0813360ca76f509805a76dc6330e34d431700734 100644 (file)
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)    += wrpll-cln28hpc.o
-
 obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)            += fu540-prci.o
 
 obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT)           += gemgxl-mgmt.o
index 2d47ebc6b1ea6aa5e18f931295c66d4317a382e0..56084db2e6ac2ab89b185233c3dcc26872d5c83b 100644 (file)
 #include <errno.h>
 
 #include <linux/math64.h>
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
 #include <dt-bindings/clk/sifive-fu540-prci.h>
 
-#include "analogbits-wrpll-cln28hpc.h"
-
 /*
  * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
  *     hfclk and rtcclk