]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ram: rk3399: add missing high row detection
authorJonathan Liu <net147@gmail.com>
Thu, 23 Mar 2023 10:35:58 +0000 (21:35 +1100)
committerKever Yang <kever.yang@rock-chips.com>
Fri, 21 Apr 2023 07:16:01 +0000 (15:16 +0800)
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"

U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"

Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"

Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
drivers/ram/rockchip/sdram_rk3399.c

index 963a05c244a6514204d0185d7257554572c3988b..899324525208151950cdd0cd750c8c7da4b00e7e 100644 (file)
@@ -2749,6 +2749,8 @@ static u64 dram_detect_cap(struct dram_info *dram,
        /* detect cs1 row */
        sdram_detect_cs1_row(cap_info, params->base.dramtype);
 
+       sdram_detect_high_row(cap_info);
+
        /* detect die bw */
        sdram_detect_dbw(cap_info, params->base.dramtype);