mx6: clock: Add thermal clock enable function

Add api to check and enable pll3 as required
for thermal sensor driver.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 6c9c78c11a11ea24f9d494e96630dc0bf238f333..80b11aaf505fe5ca006ad04c51da9b2a735c54e1 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -673,6 +673,36 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+static void enable_pll3(void)
+{
+       struct anatop_regs __iomem *anatop =
+               (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+       /* make sure pll3 is enabled */
+       if ((readl(&anatop->usb1_pll_480_ctrl) &
+                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+               /* enable pll's power */
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+                      &anatop->usb1_pll_480_ctrl_set);
+               writel(0x80, &anatop->ana_misc2_clr);
+               /* wait for pll lock */
+               while ((readl(&anatop->usb1_pll_480_ctrl) &
+                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+                       ;
+               /* disable bypass */
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+                      &anatop->usb1_pll_480_ctrl_clr);
+               /* enable pll output */
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+                      &anatop->usb1_pll_480_ctrl_set);
+       }
+}
+
+void enable_thermal_clk(void)
+{
+       enable_pll3();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {

diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 3c58a0ab6041897794d28ac514dd7ab2fe256949..8e51f9b3a0edb34cc0561acdc9f20e4ec6bd81e2 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -66,4 +66,5 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */