crypto/fsl: i.MX8: Enable Job ring driver model.

i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 79b80467f7f6a99455a7fe0a692a7c26dda78656..efe33a58e1eff272a5884f71bec6a224cae2c08f 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -853,6 +853,9 @@ config ARCH_LPC32XX
 config ARCH_IMX8
        bool "NXP i.MX8 platform"
        select ARM64
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_4
+       select SYS_FSL_SEC_LE
        select DM
        select GPIO_EXTRA_HEADER
        select MACH_IMX

diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e5569de08eac42002d21fa88e00a9b8315..2d64b0604b92e33a9ec2900568dcf38456a86887 100644 (file)
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #ifndef __ASM_ARCH_IMX8_REGS_H__
@@ -47,4 +47,7 @@
 #define USB_BASE_ADDR          0x5b0d0000
 #define USB_PHY0_BASE_ADDR     0x5b100000
 
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
 #endif /* __ASM_ARCH_IMX8_REGS_H__ */

diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 89da89c51d5b8c2a3a832e1d087bcd2237ab4301..04c4b20a84bc257a7d1f3bbd56df5bcaec7785c8 100644 (file)
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -9,6 +9,7 @@
 #include <command.h>
 #include <log.h>
 #include <malloc.h>
+#include <memalign.h>
 #include <asm/byteorder.h>
 #include <linux/compiler.h>
 #include <fsl_sec.h>

diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c64dcaa711bde3f75b6a4fa72dd0412b..f969833babab54bd1ea7fe87c7a6053d798f0948 100644 (file)
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -8,6 +8,7 @@ config AHAB_BOOT
 
 config IMX8
        bool
+       select HAS_CAAM
 
 config MU_BASE_SPL
        hex "MU base address used in SPL"
@@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK
        bool "Support i.MX8QM MEK board"
        select BOARD_LATE_INIT
        select IMX8QM
+       select FSL_CAAM
+       select ARCH_MISC_INIT
+       select SPL_CRYPTO if SPL
 
 config TARGET_CONGA_QMX8
        bool "Support congatec conga-QMX8 board"
@@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK
        bool "Support i.MX8QXP MEK board"
        select BOARD_LATE_INIT
        select IMX8QXP
+       select FSL_CAAM
+       select ARCH_MISC_INIT
+       select SPL_CRYPTO if SPL
 
 endchoice
 

diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 359f8c796eb35b41e920af43effe6a1cb79554b8..0858ea5f0575c76da8a627b60ea4934a3abb10d9 100644 (file)
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <common.h>
@@ -91,6 +91,22 @@ static int imx8_init_mu(void *ctx, struct event *event)
 }
 EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
 
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+       if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+               struct udevice *dev;
+               int ret;
+
+               ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+               if (ret)
+                       printf("Failed to initialize %s: %d\n", dev->name, ret);
+       }
+
+       return 0;
+}
+#endif
+
 int print_bootinfo(void)
 {
        enum boot_device bt_dev = get_boot_device();

diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 944ba745c09ffaebfeb71522d9fb41c36e2167d0..332a662dee843353f7d7729ceb0710e42859eb15 100644 (file)
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -24,6 +24,8 @@ void spl_board_init(void)
 {
        struct udevice *dev;
 
+       uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
        uclass_find_first_device(UCLASS_MISC, &dev);
 
        for (; dev; uclass_find_next_device(&dev)) {

diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index ae6b64ff6ea120018d2c698b0e94027e6105ab79..2fa68400561331001b450c140b8101b55ac11be1 100644 (file)
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -39,6 +39,8 @@ void spl_board_init(void)
 {
        struct udevice *dev;
 
+       uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
        uclass_find_first_device(UCLASS_MISC, &dev);
 
        for (; dev; uclass_find_next_device(&dev)) {

diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 231eb00b5fea54fea10dcc73176bcca24b1e64a9..e03fcdd9c7e49c621d801286a5146f9757bf6fab 100644 (file)
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -12,7 +12,7 @@ config FSL_CAAM
 
 config CAAM_64BIT
        bool
-       default y if PHYS_64BIT && !ARCH_IMX8M
+       default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
        help
          Select Crypto driver for 64 bits CAAM version
 

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 810398742523cf2cd5a822b50686d52a5adce444..1d951cf0a64f16424a3b68b03445ac0854983926 100644 (file)
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <log.h>
 #include <malloc.h>
+#include <power-domain.h>
 #include "jr.h"
 #include "jobdesc.h"
 #include "desc_constr.h"
@@ -113,7 +114,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
 static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
 {
        struct jobring *jr = &caam->jr[sec_idx];
-
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+       ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+#endif
        memset(jr, 0, sizeof(struct jobring));
 
        jr->jq_id = caam->jrid;
@@ -138,7 +141,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
        memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
        memset(jr->output_ring, 0, jr->op_size);
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+       if (!ofnode_valid(scu_node))
+#endif
        start_jr(caam);
+
        jr_initregs(sec_idx, caam);
 
        return 0;
@@ -673,6 +680,13 @@ int sec_init_idx(uint8_t sec_idx)
        caam_st.jrid = 0;
        caam = &caam_st;
 #endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+       ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+
+       if (ofnode_valid(scu_node))
+               goto init;
+#endif
+
        ccsr_sec_t *sec = caam->sec;
        uint32_t mcr = sec_in32(&sec->mcfgr);
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
@@ -734,12 +748,19 @@ int sec_init_idx(uint8_t sec_idx)
        liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
        liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 #endif
+#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+init:
 #endif
        ret = jr_init(sec_idx, caam);
        if (ret < 0) {
                printf("SEC%u:  initialization failed\n", sec_idx);
                return -1;
        }
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+       if (ofnode_valid(scu_node))
+               return ret;
+#endif
 
 #ifdef CONFIG_FSL_CORENET
        ret = sec_config_pamu_table(liodn_ns, liodn_s);
@@ -773,6 +794,23 @@ int sec_init(void)
 }
 
 #if CONFIG_IS_ENABLED(DM)
+static int jr_power_on(ofnode node)
+{
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+       struct udevice __maybe_unused jr_dev;
+       struct power_domain pd;
+
+       dev_set_ofnode(&jr_dev, node);
+
+       /* Power on Job Ring before access it */
+       if (!power_domain_get(&jr_dev, &pd)) {
+               if (power_domain_on(&pd))
+                       return -EINVAL;
+       }
+#endif
+       return 0;
+}
+
 static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
 {
        if (request != CAAM_JR_RUN_DESC)
@@ -785,7 +823,7 @@ static int caam_jr_probe(struct udevice *dev)
 {
        struct caam_regs *caam = dev_get_priv(dev);
        fdt_addr_t addr;
-       ofnode node;
+       ofnode node, scu_node;
        unsigned int jr_node = 0;
 
        caam_dev = dev;
@@ -810,6 +848,11 @@ static int caam_jr_probe(struct udevice *dev)
                                jr_node = jr_node >> 4;
 
                        caam->jrid = jr_node - 1;
+                       scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+                       if (ofnode_valid(scu_node)) {
+                               if (jr_power_on(node))
+                                       return -EINVAL;
+                       }
                        break;
                }
        }

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c4121696f82c2f7936c3e240f434e77d0853ef17..7b6e3e2c20d7d6e1e6d5c78c7deccba2b236c798 100644 (file)
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,7 +3,7 @@
  * Common internal memory map for some Freescale SoCs
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #ifndef __FSL_SEC_H
@@ -194,12 +194,10 @@ typedef struct ccsr_sec {
 #define SEC_CHAVID_LS_RNG_SHIFT                16
 #define SEC_CHAVID_RNG_LS_MASK         0x000f0000
 
-#define CONFIG_JRSTARTR_JR0            0x00000001
-
 struct jr_regs {
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
        u32 irba_l;
        u32 irba_h;
 #else
@@ -214,7 +212,7 @@ struct jr_regs {
        u32 irja;
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
        u32 orba_l;
        u32 orba_h;
 #else
@@ -248,7 +246,7 @@ struct jr_regs {
 struct sg_entry {
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
        uint32_t addr_lo;       /* Memory Address - lo */
        uint32_t addr_hi;       /* Memory Address of start of buffer - hi */
 #else
@@ -268,7 +266,7 @@ struct sg_entry {
 };
 
 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-       defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+       defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
 /* Job Ring Base Address */
 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
 /* Secure Memory Offset varies accross versions */