armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A

Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 8675e91fca07e260ea3a25fc729d778cc3e7772c..032cfd80ebbeb4f174471228399bb7837ccc9b47 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -10,6 +10,7 @@
 #include <fsl_ddrc_version.h>
 
 #define CONFIG_SYS_PAGE_SIZE           0x10000
+#define CONFIG_SYS_CACHELINE_SIZE      64
 
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6