This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
config TARGET_IP860
bool "Support IP860"
-config TARGET_IVML24
- bool "Support IVML24"
-
-config TARGET_IVMS8
- bool "Support IVMS8"
-
config TARGET_TQM823L
bool "Support TQM823L"
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
-source "board/ivm/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
*/
#if defined(CONFIG_IP860) || \
- defined(CONFIG_IVML24) || \
- defined(CONFIG_IVMS8) || \
defined(CONFIG_RMU)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
+++ /dev/null
-if TARGET_IVML24
-
-config SYS_BOARD
- default "ivm"
-
-config SYS_CONFIG_NAME
- default "IVML24"
-
-endif
-
-if TARGET_IVMS8
-
-config SYS_BOARD
- default "ivm"
-
-config SYS_CONFIG_NAME
- default "IVMS8"
-
-endif
+++ /dev/null
-IVM BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/ivm/
-F: include/configs/IVML24.h
-F: configs/IVML24_defconfig
-F: configs/IVML24_128_defconfig
-F: configs/IVML24_256_defconfig
-F: include/configs/IVMS8.h
-F: configs/IVMS8_defconfig
-F: configs/IVMS8_128_defconfig
-F: configs/IVMS8_256_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ivm.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,
- size_b0, size_b0<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
- BR_MS_GPCM | BR_PS_16 | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_MT:
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + ((i-3) * 0x00020000);
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
- return;
-
- case FLASH_MAN_SST:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00002000);
- }
- return;
-
- case FLASH_MAN_AMD:
- case FLASH_MAN_FUJ:
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
- return;
- default:
- printf ("Don't know sector ofsets for flash type 0x%lx\n",
- info->flash_id);
- return;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_MT: printf ("MT "); break;
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n");
- break;
- case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n");
- break;
- case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n");
- break;
- case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n");
- break;
- case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n");
- break;
- case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n");
- break;
- case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1 << 20)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- ushort value;
- vu_short *saddr = (vu_short *)addr;
-
- /* Read Manufacturer ID */
- saddr[0] = 0x0090;
- value = saddr[0];
-
- switch (value) {
- case (AMD_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (SST_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (STM_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (MT_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_MT;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- saddr[0] = 0x00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- value = saddr[1]; /* device ID */
-
- switch (value) {
- case (AMD_ID_LV400T & 0xFFFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & 0xFFFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & 0xFFFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & 0xFFFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160T & 0xFFFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & 0xFFFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFFFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_LV320B & 0xFFFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- case (SST_ID_xF200A & 0xFFFF):
- info->flash_id += FLASH_SST200A;
- info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */
- info->size = 0x00080000;
- break;
- case (SST_ID_xF400A & 0xFFFF):
- info->flash_id += FLASH_SST400A;
- info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */
- info->size = 0x00100000;
- break;
- case (SST_ID_xF800A & 0xFFFF):
- info->flash_id += FLASH_SST800A;
- info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (STM_ID_x800AB & 0xFFFF):
- info->flash_id += FLASH_STM800AB;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (MT_ID_28F400_T & 0xFFFF):
- info->flash_id += FLASH_28F400_T;
- info->sector_count = 7;
- info->size = 0x00080000;
- break; /* => 512 kB */
- case (MT_ID_28F400_B & 0xFFFF):
- info->flash_id += FLASH_28F400_B;
- info->sector_count = 7;
- info->size = 0x00080000;
- break; /* => 512 kB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- saddr[0] = 0x00FF; /* restore read mode */
- return (0); /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- saddr[0] = 0x00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) {
- printf ("Can erase only MT flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_short *addr = (vu_short *)(info->start[sect]);
- unsigned short status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x0050; /* clear status register */
- *addr = 0x0020; /* erase setup */
- *addr = 0x00D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & 0x0080) != 0x0080) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0x00FF; /* reset to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = 0x00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 2 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<FLASH_WIDTH && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i=0; i<FLASH_WIDTH; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, ulong data)
-{
- vu_short *addr = (vu_short *)dest;
- ushort sdata = (ushort)data;
- ushort status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & sdata) != sdata) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x0040; /* write setup */
- *addr = sdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (((status = *addr) & 0x0080) != 0x0080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0x00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = 0x00FF; /* restore read mode */
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-
-#ifdef CONFIG_STATUS_LED
-# include <status_led.h>
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*
- * 50 MHz SHARC access using UPM A
- */
-const uint sharc_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-/*
- * 50 MHz SDRAM access using UPM B
- */
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
- _NOT_USED_,
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
- 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
- 0xE1BBBC04, 0x1FF77C45, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
- 0xFFFFFC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- */
-
-int checkboard (void)
-{
-#ifdef CONFIG_IVMS8
- puts ("Board: IVMS8\n");
-#endif
-#ifdef CONFIG_IVML24
- puts ("Board: IVM-L8/24\n");
-#endif
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0;
-
- /* enable SDRAM clock ("switch on" SDRAM) */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
- udelay (1);
-
- /*
- * Map controller bank 1 for ELIC SACCO
- */
- memctl->memc_or1 = CONFIG_SYS_OR1;
- memctl->memc_br1 = CONFIG_SYS_BR1;
-
- /*
- * Map controller bank 2 for ELIC EPIC
- */
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
-
- /*
- * Configure UPMA for SHARC
- */
- upmconfig (UPMA, (uint *) sharc_table,
- sizeof (sharc_table) / sizeof (uint));
-
-#if defined(CONFIG_IVML24)
- /*
- * Map controller bank 4 for HDLC Address space
- */
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-#endif
-
- /*
- * Map controller bank 5 for SHARC
- */
- memctl->memc_or5 = CONFIG_SYS_OR5;
- memctl->memc_br5 = CONFIG_SYS_BR5;
-
- memctl->memc_mamr = 0x00001000;
-
- /*
- * Configure UPMB for SDRAM
- */
- upmconfig (UPMB, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
-
- udelay (200);
- memctl->memc_mcr = 0x80806105; /* precharge */
- udelay (1);
- memctl->memc_mcr = 0x80806106; /* load mode register */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
-
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 =
- dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
- SDRAM_MAX_SIZE);
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- memctl->memc_mbmr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phy (void)
-{
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay (1000);
-
- /*
- * RESET is implemented by a positive pulse of at least 1 us
- * at the reset pin.
- *
- * Configure RESET pins for NS DP83843 PHY, and RESET chip.
- *
- * Note: The RESET pin is high active, but there is an
- * inverter on the SPD823TS board...
- */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
- /* assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
- udelay (10);
- /* de-assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
- udelay (10);
-}
-
-/* ------------------------------------------------------------------------- */
-
-void show_boot_progress (int status)
-{
-#if defined(CONFIG_STATUS_LED)
-# if defined(STATUS_LED_YELLOW)
- status_led_set (STATUS_LED_YELLOW,
- (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
-# endif /* STATUS_LED_YELLOW */
-# if defined(STATUS_LED_BOOT)
- if (status == BOOTSTAGE_ID_DECOMP_IMAGE)
- status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
-# endif /* STATUS_LED_BOOT */
-#endif /* CONFIG_STATUS_LED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-void ide_set_reset (int on)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- int i;
-
- /*
- * Configure PC for IDE Reset Pin
- */
- if (on) { /* assert RESET */
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
-
-#ifdef CONFIG_SYS_PB_12V_ENABLE
- /* 12V Enable output OFF */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
-
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
-
- /* wait 500 ms for the voltage to stabilize */
- for (i = 0; i < 500; ++i)
- udelay(1000);
-#endif /* CONFIG_SYS_PB_12V_ENABLE */
- } else { /* release RESET */
-#ifdef CONFIG_SYS_PB_12V_ENABLE
- /* 12V Enable output ON */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
-#endif /* CONFIG_SYS_PB_12V_ENABLE */
-
-#ifdef CONFIG_SYS_PB_IDE_MOTOR
- /* configure IDE Motor voltage monitor pin as input */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
-
-/* wait up to 1 s for the motor voltage to stabilize */
- for (i = 0; i < 1000; ++i) {
- if ((immr->im_cpm.cp_pbdat
- & CONFIG_SYS_PB_IDE_MOTOR) != 0)
- break;
- udelay(1000);
- }
-
- if (i == 1000) { /* Timeout */
- printf("\nWarning: 5V for IDE Motor missing\n");
-#ifdef CONFIG_STATUS_LED
-#ifdef STATUS_LED_YELLOW
- status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
-#endif
-#ifdef STATUS_LED_GREEN
- status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
-#endif
-#endif /* CONFIG_STATUS_LED */
- }
-#endif /* CONFIG_SYS_PB_IDE_MOTOR */
-
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
- }
-
- /* program port pin as GPIO output */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IVML24_32M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVML24=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IVML24_64M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVML24=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IVML24_16M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVML24=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IVMS8_32M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVMS8=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IVMS8_64M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVMS8=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IVMS8_16M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVMS8=y
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+IVMS8 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
lwmon powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
#define SICR_ENET_CLKRT ((uint)0x0000002C)
#endif /* CONFIG_IP860 */
-/*** IVMS8 **********************************************************/
-
-/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
-
-#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
-
-#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
-
/*** KM8XX *********************************************************/
/* The KM8XX Service Module uses SCC3 for Ethernet */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_IVML24 1 /* ...on a IVML24 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_IDENT_STRING " IVML24"
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_IDENT_STRING " IVML24_128"
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_IDENT_STRING " IVML24_256"
-#endif
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ 50331648
-
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */
-#define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */
-#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
-#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
-
-#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
-#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-
-# if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-# elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# endif
-
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00B0C0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800014 */
-#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD101 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CONFIG_SYS_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
-#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_SACCO_BASE 0xFE000000
-#define ELIC_SACCO_OR_AM 0xFFFF8000
-#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
-
-#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- ELIC_SACCO_TIMING)
-#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_EPIC_BASE 0xFE008000
-#define ELIC_EPIC_OR_AM 0xFFFF8000
-#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
-
-#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- ELIC_EPIC_TIMING)
-#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4 - HDLC Address
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
- */
-#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */
-#define HDLC_ADDR_OR_AM 0xFFFF8000
-#define HDLC_ADDR_TIMING OR_SCY_1_CLK
-
-#define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
-#define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
-
-/*
- * BR5/OR5: SHARC ADSP-2165L
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define SHARC_BASE 0xFE400000
-#define SHARC_OR_AM 0xFFC00000
-#define SHARC_TIMING OR_SCY_0_CLK
-
-#define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
-#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MBMR_PTB 204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
-#endif
-
-
-/*
- * MBMR settings for SDRAM
- */
-
-#if defined (CONFIG_IVML24_16M)
- /* 8 column SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVML24_32M)
-/* 128 MBit SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVML24_64M)
-/* 128 MBit SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#endif
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#if defined (CONFIG_IVMS8_16M)
-# define CONFIG_IDENT_STRING " IVMS8"
-#elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_IDENT_STRING " IVMS8_128"
-#elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_IDENT_STRING " IVMS8_256"
-#endif
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ 50331648
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
-#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
-
-#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
-#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#if defined (CONFIG_IVMS8_16M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-# if defined (CONFIG_IVMS8_16M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-# elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# endif
-#else
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00B0C0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800014 */
-#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD101 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CONFIG_SYS_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
-#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_SACCO_BASE 0xFE000000
-#define ELIC_SACCO_OR_AM 0xFFFF8000
-#define ELIC_SACCO_TIMING 0x00000F26
-
-#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
-#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_EPIC_BASE 0xFE008000
-#define ELIC_EPIC_OR_AM 0xFFFF8000
-#define ELIC_EPIC_TIMING 0x00000F26
-
-#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
-#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4: not used
- */
-
-/*
- * BR5/OR5: SHARC ADSP-2165L
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define SHARC_BASE 0xFE400000
-#define SHARC_OR_AM 0xFFC00000
-#define SHARC_TIMING 0x00000700
-
-#define CONFIG_SYS_OR5 (SHARC_OR_AM | SHARC_TIMING )
-#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MBMR_PTB 204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#if defined (CONFIG_IVMS8_16M)
- #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVMS8_32M)
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVMS8_64M)
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
-#endif
-
-
-/*
- * MBMR settings for SDRAM
- */
-
-#if defined (CONFIG_IVMS8_16M)
- /* 8 column SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVMS8_32M)
-/* 128 MBit SDRAM */
-#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVMS8_64M)
-/* 128 MBit SDRAM */
-#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-
-#endif
-#endif /* __CONFIG_H */
#if defined(CONFIG_TQM8xxL)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
-#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
-# define CONFIG_PCMCIA_SLOT_A
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
#else
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** IVMS8 **********************************************************/
-#elif defined(CONFIG_IVMS8)
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
-# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
-# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-/* IDE LED usable for other purposes, too */
-# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
-# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
-
-# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
-
-# define STATUS_LED_YELLOW 0
-# define STATUS_LED_GREEN 1
-# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-
-/***** IVML24 *********************************************************/
-#elif defined(CONFIG_IVML24)
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
-# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
-# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-/* IDE LED usable for other purposes, too */
-# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
-# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
-
-# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
-
-# define STATUS_LED_YELLOW 0
-# define STATUS_LED_GREEN 1
-# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-
/***** Someone else defines these *************************************/
#elif defined(STATUS_LED_PAR)
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