ARM: DRA7: emif: Fix DDR init sequence during warm reset

Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.

Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index ca22c0060182d776c3240e7632b0e4544e9697b2..f5b22f6a783626590f06123050437e8d3ad14b21 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1170,7 +1170,7 @@ static void do_sdram_init(u32 base)
         * Changing the timing registers in EMIF can happen(going from one
         * OPP to another)
         */
-       if (!(in_sdram || warm_reset())) {
+       if (!in_sdram && (!warm_reset() || is_dra7xx())) {
                if (emif_sdram_type(regs->sdram_config) ==
                    EMIF_SDRAM_TYPE_LPDDR2)
                        lpddr2_init(base, regs);
@@ -1178,7 +1178,7 @@ static void do_sdram_init(u32 base)
                        ddr3_init(base, regs);
        }
        if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
-           EMIF_SDRAM_TYPE_DDR3)) {
+           EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
                set_lpmode_selfrefresh(base);
                emif_reset_phy(base);
                omap5_ddr3_leveling(base, regs);