riscv: ae350: Enable CCTL_SUEN

CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index c4c2de2ef053d9b4e8d9904ecfa2278922c73de1..a46674f7c2585d5fc86f9ce57ea2bc073718387e 100644 (file)
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -12,18 +12,20 @@
 #include <asm/csr.h>
 
 #define CSR_MCACHE_CTL 0x7ca
-#define CSR_MMISC_CTL  0x7d0
-#define CSR_MARCHID            0xf12
+#define CSR_MMISC_CTL          0x7d0
+#define CSR_MARCHID                    0xf12
 
 #define V5_MCACHE_CTL_IC_EN_OFFSET      0
 #define V5_MCACHE_CTL_DC_EN_OFFSET      1
-#define V5_MCACHE_CTL_DC_COHEN_OFFSET  19
+#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET          19
 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
 
-#define V5_MCACHE_CTL_IC_EN            BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN                            BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHEN_EN       BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHSTA_EN      BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+#define V5_MCACHE_CTL_IC_EN                                    BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN                                    BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_CCTL_SUEN                        BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN   BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN  BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
 
 
 /*
@@ -55,6 +57,8 @@ void harts_early_init(void)
                        mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
                if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
                        mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+               if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
+                       mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
                csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
 
                /*