mpc85xx/T1040QDS_D4: Add DDR4 support

T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index da89a36b96ad58b23aacf68f3c9f85c123dd95f6..43f952f9c03b4e8fc21d5854adf5e48a510993a7 100644 (file)
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -39,14 +39,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                if (pbsp->n_ranks == pdimm->n_ranks &&
                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
                        if (ddr_freq <= pbsp->datarate_mhz_high) {
-                               popts->cpo_override = pbsp->cpo;
-                               popts->write_data_delay =
-                                       pbsp->write_data_delay;
                                popts->clk_adjust = pbsp->clk_adjust;
                                popts->wrlvl_start = pbsp->wrlvl_start;
                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-                               popts->twot_en = pbsp->force_2t;
                                goto found;
                        }
                        pbsp_highest = pbsp;
@@ -59,13 +55,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                printf("for data rate %lu MT/s\n", ddr_freq);
                printf("Trying to use the highest speed (%u) parameters\n",
                       pbsp_highest->datarate_mhz_high);
-               popts->cpo_override = pbsp_highest->cpo;
-               popts->write_data_delay = pbsp_highest->write_data_delay;
                popts->clk_adjust = pbsp_highest->clk_adjust;
                popts->wrlvl_start = pbsp_highest->wrlvl_start;
                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-               popts->twot_en = pbsp_highest->force_2t;
        } else {
                panic("DIMM is not supported by this board");
        }
@@ -81,7 +74,7 @@ found:
         * Factors to consider for half-strength driver enable:
         *      - number of DIMMs installed
         */
-       popts->half_strength_driver_enable = 0;
+       popts->half_strength_driver_enable = 1;
        /*
         * Write leveling override
         */
@@ -97,8 +90,14 @@ found:
        popts->zq_en = 1;
 
        /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+                         DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 phys_size_t initdram(int board_type)

diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
index afa72af26a6c368c48f4d012e089b6d2663d884e..a6e1673525f5d3cc50f1c1e2ab2e3f610c5c8434 100644 (file)
--- a/board/freescale/t1040qds/ddr.h
+++ b/board/freescale/t1040qds/ddr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -14,9 +14,6 @@ struct board_specific_parameters {
        u32 wrlvl_start;
        u32 wrlvl_ctl_2;
        u32 wrlvl_ctl_3;
-       u32 cpo;
-       u32 write_data_delay;
-       u32 force_2t;
 };
 
 /*
@@ -28,21 +25,25 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
        /*
         * memory controller 0
-        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
-       {2,  833,  4, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
-       {2,  833,  0, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
-       {2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
-       {2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
-       {2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
-       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
-       {1,  833,  4, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
-       {1,  833,  0, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
-       {1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
-       {1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
-       {1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
-       {1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
+#ifdef CONFIG_SYS_FSL_DDR4
+       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+       {2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+       {1,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
+       {1,  2200, 0, 4,     7, 0x08090A0D, 0x0F0F100C,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+       {2,  833,  0, 4,     6, 0x06060607, 0x08080807,},
+       {2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
+       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+       {1,  833,  0, 4,     6, 0x06060607, 0x08080807,},
+       {1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
+       {1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+#else
+#error DDR type not defined
+#endif
        {}
 };
 

diff --git a/boards.cfg b/boards.cfg
index 730066c9688b04ea32ed6f03bcdb57b4d58c7df9..f6837b767cb20b15f49169d79a5280664fb49a93 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -942,6 +942,7 @@ Active  powerpc     mpc85xx        -           freescale       p2041rdb
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SPIFLASH                    P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                            -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SRIO_PCIE_BOOT              P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                            -
 Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS                             T1040QDS:PPC_T1040                                                                                                                Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS_D4                          T1040QDS:PPC_T1040,SYS_FSL_DDR4                                                                                                   Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS_SECURE_BOOT                 T1040QDS:PPC_T1040,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1040RDB                             T1040RDB:PPC_T1040                                                                                                                Poonam Aggrwal  <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1040RDB_SECURE_BOOT                 T1040RDB:PPC_T1040,SECURE_BOOT                                                                                                    Aneesh Bansal  <aneesh.bansal@freescale.com>

diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 84213b8eaf106aa18e079658c09534843090522a..63a7efccf231455d53b87c7e12aa3aedcf37014b 100644 (file)
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -169,8 +169,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
+#endif
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x51