imx8mn: Add support for 11x11 UltraLite part number

There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo

Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index f37fe214460fec2da3631edcaedf8795e1407176..28244d767189165d6cb1db422f952e5e9249b7ba 100644 (file)
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -40,10 +40,13 @@
 #define MXC_CPU_IMX8MNL                0x8e /* dummy ID */
 #define MXC_CPU_IMX8MNDL               0x8f /* dummy ID */
 #define MXC_CPU_IMX8MNSL               0x181 /* dummy ID */
-#define MXC_CPU_IMX8MP         0x182/* dummy ID */
-#define MXC_CPU_IMX8MP6                0x184 /* dummy ID */
-#define MXC_CPU_IMX8MPL                0x186 /* dummy ID */
-#define MXC_CPU_IMX8MPD                0x187 /* dummy ID */
+#define MXC_CPU_IMX8MNUQ               0x182 /* dummy ID */
+#define MXC_CPU_IMX8MNUD               0x183 /* dummy ID */
+#define MXC_CPU_IMX8MNUS               0x184 /* dummy ID */
+#define MXC_CPU_IMX8MP         0x185/* dummy ID */
+#define MXC_CPU_IMX8MP6                0x186 /* dummy ID */
+#define MXC_CPU_IMX8MPL                0x187 /* dummy ID */
+#define MXC_CPU_IMX8MPD                0x188 /* dummy ID */
 #define MXC_CPU_IMX8QXP_A0     0x90 /* dummy ID */
 #define MXC_CPU_IMX8QM         0x91 /* dummy ID */
 #define MXC_CPU_IMX8QXP                0x92 /* dummy ID */

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 43eae6d796d9e682203d44ec5655d1fe19475f06..c7668ffc4d89c8264a00059aff2db8e3013726cf 100644 (file)
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -60,12 +60,16 @@ struct bd_info;
 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
        is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
-       is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL))
+       is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
+       is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
+#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
+#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
+#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)  || is_cpu_type(MXC_CPU_IMX8MPD) || \
        is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 38b87ed5c39a9daf0251c7f52d3d68addd297087..423b7153522a724dd78ddcb7200fce3ba68ca6b4 100644 (file)
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -117,7 +117,13 @@ const char *get_imx_type(u32 imxtype)
        case MXC_CPU_IMX8MNDL:
                return "8MNano DualLite"; /* Dual-core Lite version */
        case MXC_CPU_IMX8MNSL:
-               return "8MNano SoloLite"; /* Single-core Lite version */
+               return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
+       case MXC_CPU_IMX8MNUQ:
+               return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
+       case MXC_CPU_IMX8MNUD:
+               return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
+       case MXC_CPU_IMX8MNUS:
+               return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
        case MXC_CPU_IMX8MM:
                return "8MMQ";  /* Quad-core version of the imx8mm */
        case MXC_CPU_IMX8MML:

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 1a752d8fd8a96147e8d7aa5834f49668bb4a262a..cda3a593ae77b36ba90d2118f6bc92e2c977082e 100644 (file)
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -324,18 +324,30 @@ static u32 get_cpu_variant_type(u32 type)
        } else if (type == MXC_CPU_IMX8MN) {
                switch (value & 0x3) {
                case 2:
-                       if (value & 0x1000000)
-                               return MXC_CPU_IMX8MNDL;
-                       else
+                       if (value & 0x1000000) {
+                               if (value & 0x10000000)  /* MIPI DSI */
+                                       return MXC_CPU_IMX8MNUD;
+                               else
+                                       return MXC_CPU_IMX8MNDL;
+                       } else {
                                return MXC_CPU_IMX8MND;
+                       }
                case 3:
-                       if (value & 0x1000000)
-                               return MXC_CPU_IMX8MNSL;
-                       else
+                       if (value & 0x1000000) {
+                               if (value & 0x10000000)  /* MIPI DSI */
+                                       return MXC_CPU_IMX8MNUS;
+                               else
+                                       return MXC_CPU_IMX8MNSL;
+                       } else {
                                return MXC_CPU_IMX8MNS;
+                       }
                default:
-                       if (value & 0x1000000)
-                               return MXC_CPU_IMX8MNL;
+                       if (value & 0x1000000) {
+                               if (value & 0x10000000)  /* MIPI DSI */
+                                       return MXC_CPU_IMX8MNUQ;
+                               else
+                                       return MXC_CPU_IMX8MNL;
+                       }
                        break;
                }
        } else if (type == MXC_CPU_IMX8MP) {
@@ -468,7 +480,7 @@ int arch_cpu_init(void)
 
                if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
                    is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
-                   is_imx8mnsl() || is_imx8mpd()) {
+                   is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
                        /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
                        struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
                        struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
@@ -477,7 +489,7 @@ int arch_cpu_init(void)
 
                        writel(0x1, &pgc_core2->pgcr);
                        writel(0x1, &pgc_core3->pgcr);
-                       if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
+                       if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
                                writel(0x1, &pgc_core1->pgcr);
                                writel(0xE, &gpc->cpu_pgc_dn_trg);
                        } else {
@@ -941,9 +953,9 @@ usb_modify_speed:
        }
 #endif
 
-       if (is_imx8mnd() || is_imx8mndl())
+       if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
                disable_cpu_nodes(blob, 2);
-       else if (is_imx8mns() || is_imx8mnsl())
+       else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
                disable_cpu_nodes(blob, 3);
 
 #elif defined(CONFIG_IMX8MP)