MIPS: mips32/cache.S: save return address in t9 register

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 40bb46e5b68bf25d9d3ad860ba9714d22f64dc14..fc13d3faab9d2f14da49e3f3dcbb9a7d76e65fd3 100644 (file)
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -18,7 +18,7 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
-#define RA             t8
+#define RA             t9
 
 /*
  * 16kB is the maximum size of instruction and data caches on MIPS 4K,