arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux

To synchronise the device tree in U-Boot with Linux, the GIC
(Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised
before changing any dependent components like PCIe and DPAA2/fsl-mc.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 3afd847baf1b4beb081e9b83f05a8534a40bab9b..05da798380a24ff462548440a45b7821877c04c9 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -15,11 +15,23 @@
 
        gic: interrupt-controller@6000000 {
                compatible = "arm,gic-v3";
-               reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
-                     <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
                #interrupt-cells = <3>;
                interrupt-controller;
-               interrupts = <1 9 0x4>;
+               reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+                     <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
+                     <0x0 0x0c0c0000 0 0x2000>, /* GICC */
+                     <0x0 0x0c0d0000 0 0x1000>, /* GICH */
+                     <0x0 0x0c0e0000 0 0x20000>; /* GICV */
+               interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               its: gic-its@6020000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0x6020000 0 0x20000>;
+               };
        };
 
        timer {
@@ -68,6 +80,97 @@
                        interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
+
+               smmu: iommu@5000000 {
+                       compatible = "arm,mmu-500";
+                       reg = <0 0x5000000 0 0x800000>;
+                       #iommu-cells = <1>;
+                       stream-match-mask = <0x7C00>;
+                       dma-coherent;
+                       #global-interrupts = <12>;
+                                    // global secure fault
+                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    // combined secure
+                                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                    // global non-secure fault
+                                    <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                    // combined non-secure
+                                    <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                    // performance counter interrupts 0-7
+                                    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+                                    // per context interrupt, 64 interrupts
+                                    <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+               };
        };
 
        i2c0: i2c@2000000 {