mpc86xx: Use SRR0/1/rfi to enable address translation, not blr

Using a mtmsr/blr means that you have to be executing at the
same virtual address once you enable translation.  This is
unnecessarily restrictive, and is not really how this is
usually done.  Change it to use the more common mtspr SRR0/SRR1
and rfi method.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0d30e91b61c47447e76a3c00f68d69009addf178..7e36801741c90561423b32b054516ad90c6ec7b0 100644 (file)
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -244,9 +244,15 @@ in_flash:
         */
 
        /* enable address translation */
-       bl      enable_addr_trans
-       sync
+       mfmsr   r5
+       ori     r5, r5, (MSR_IR | MSR_DR)
+       lis     r3,addr_trans_enabled@h
+       ori     r3, r3, addr_trans_enabled@l
+       mtspr   SPRN_SRR0,r3
+       mtspr   SPRN_SRR1,r5
+       rfi
 
+addr_trans_enabled:
        /* enable and invalidate the data cache */
 /*     bl      l1dcache_enable */
        bl      dcache_enable
@@ -423,15 +429,6 @@ tlblp:
        blt tlblp
        blr
 
-       .globl enable_addr_trans
-enable_addr_trans:
-       /* enable address translation */
-       mfmsr   r5
-       ori     r5, r5, (MSR_IR | MSR_DR)
-       mtmsr   r5
-       isync
-       blr
-
        .globl disable_addr_trans
 disable_addr_trans:
        /* disable address translation */