board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build

AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index d4b36dbb42f3d68a2bee37da9c1cbc01a8421b32..98172c28f5d3daf08071cbb9a9db35e5bc6f9e9c 100644 (file)
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM
        bool "TI K3 based AM654 EVM running on A53"
        select ARM64
        select SOC_K3_AM6
+       select SYS_DISABLE_DCACHE_OPS
 
 config TARGET_AM654_R5_EVM
        bool "TI K3 based AM654 EVM running on R5"