armv8: fsl-lsch3: Make CCN-504 related code conditional

LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/README b/README
index c0c8b559f9bcac54a706cad7f4adf0a70550b1a2..ca07f7a3f9109e9139fd6ec4a2513bc6befe262c 100644 (file)
--- a/README
+++ b/README
@@ -322,6 +322,10 @@ build a config tool - later.
                Defined For SoC that has cache coherent interconnect
                CCN-400
 
+               CONFIG_SYS_FSL_HAS_CCN504
+
+               Defined for SoC that has cache coherent interconnect CCN-504
+
 The following options need to be configured:
 
 - CPU Type:    Define exactly one, e.g. CONFIG_MPC85XX.

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cdadd38a1242dcb7b7158de4f7773e822432711d..d72f8f84d490e07f6158de147ad11e7b3822e006 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -61,6 +61,7 @@ config ARCH_LS2080A
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
+       select SYS_FSL_HAS_CCN504
        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_DDR4
@@ -269,6 +270,9 @@ config SYS_FSL_IFC_BANK_COUNT
 config SYS_FSL_HAS_CCI400
        bool
 
+config SYS_FSL_HAS_CCN504
+       bool
+
 config SYS_FSL_HAS_DP_DDR
        bool
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 3136e3f3a2ac52d631b3d6942fbcfc904e823d91..5ff01a0e1b2cec2cdff67d5c5a64fb934b202c9e 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
        switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
 1:
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined (CONFIG_SYS_FSL_HAS_CCN504)
 
        /* Set Wuo bit for RN-I 20 */
 #ifdef CONFIG_ARCH_LS2080A
@@ -171,7 +171,7 @@ ENTRY(lowlevel_init)
        ldr     x0, =CCI_S2_QOS_CONTROL_BASE(20)
        ldr     x1, =0x00FF000C
        bl      ccn504_set_qos
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef SMMU_BASE
        /* Set the SMMU page size in the sACR register */
@@ -338,7 +338,9 @@ get_svr:
        ldr     x1, =FSL_LSCH3_SVR
        ldr     w0, [x1]
        ret
+#endif
 
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
 hnf_pstate_poll:
        /* x0 has the desired status, return 0 for success, 1 for timeout
         * clobber x1, x2, x3, x4, x6, x7
@@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
        mov     lr, x29
        ret
 ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef CONFIG_MP
        /* Keep literals not used by the secondary boot code outside it */