arm64: Fix layerscape mmu setup

With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.

On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.

Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index d1bd06bedfa06ef2750a65d293015ded6d6c9b9f..1615542a99f3f62c4228100d70e700c5eb5506ed 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -320,7 +320,7 @@ static int count_required_pts(u64 addr, int level, u64 maxaddr)
 }
 
 /* Returns the estimated required size of all page tables */
-u64 get_page_table_size(void)
+__weak u64 get_page_table_size(void)
 {
        u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
        u64 size = 0;

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 7404bd932a184c043cad8bb10611113ec0cfa0d9..4b9e209054774f647c458f44485927b4f7eae14c 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -410,6 +410,11 @@ static inline void final_mmu_setup(void)
         */
 }
 
+u64 get_page_table_size(void)
+{
+       return 0x10000;
+}
+
 int arch_cpu_init(void)
 {
        icache_enable();