arm: mach-k3: Enable dcache in SPL

Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.

Based on original patch by Lokesh Vulta.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index b692806352c89a30d0fbb43b51d641ecea377b74..586f5c022eb3ca9703af7e46b2cedeb40e918f4f 100644 (file)
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -197,6 +197,7 @@ void board_init_f(ulong dummy)
        if (ret)
                panic("DRAM init failed: %d\n", ret);
 #endif
+       spl_enable_dcache();
 }
 
 u32 spl_mmc_boot_mode(const u32 boot_device)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 80dfa5f0fd6ab398ef96489f85a6ded11407da6a..a94e054491ae907e8cdccf129badcf9333cb30c2 100644 (file)
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -406,3 +406,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
                }
        }
 }
+
+void spl_enable_dcache(void)
+{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+       phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+
+       dram_init_banksize();
+
+       /* reserve TLB table */
+       gd->arch.tlb_size = PGTABLE_SIZE;
+
+       ram_top += get_effective_memsize();
+       /* keep ram_top in the 32-bit address space */
+       if (ram_top >= 0x100000000)
+               ram_top = (phys_addr_t) 0x100000000;
+
+       gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+       debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+             gd->arch.tlb_addr + gd->arch.tlb_size);
+
+       dcache_enable();
+#endif
+}
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+void spl_board_prepare_for_boot(void)
+{
+       dcache_disable();
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+       dcache_disable();
+}
+#endif

diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 57682e19733629c09951d16800696eb18fd89ae8..94cdcb56adedbee68c3c87b72b1cb682b05d9f0f 100644 (file)
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -27,3 +27,4 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
 void start_non_linux_remote_cores(void);
 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
 void k3_sysfw_print_ver(void);
+void spl_enable_dcache(void);

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 18a3c1c0524bbdfe25270565b2f3a665797c8e2f..031279bc5b3a69757406f39cdff4107c3c6397b6 100644 (file)
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -221,6 +221,7 @@ void board_init_f(ulong dummy)
        if (ret)
                panic("DRAM init failed: %d\n", ret);
 #endif
+       spl_enable_dcache();
 }
 
 u32 spl_mmc_boot_mode(const u32 boot_device)

diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index a61087942439033b070d86ff4c2cfca44a774c71..2da7db9f096132734f162f209cf80f2b2e122110 100644 (file)
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -69,11 +69,13 @@ int dram_init_banksize(void)
        /* Bank 0 declares the memory available in the DDR low region */
        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
        gd->bd->bi_dram[0].size = 0x80000000;
+       gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
        /* Bank 1 declares the memory available in the DDR high region */
        gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
        gd->bd->bi_dram[1].size = 0x80000000;
+       gd->ram_size = 0x100000000;
 #endif
 
        return 0;