andes: cpu: Enable memboost feature

Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index e764f6c5c07e247c8fc061763635270dbdd34d6a..a23b7948d92d5920347ce70c09d350ea7b6303d0 100644 (file)
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,8 +31,11 @@ void harts_early_init(void)
        /* Enable I/D-cache in SPL */
        if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
                unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+               unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
 
-               mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
+               mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
+                               MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
+                               MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
 
                if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
                        mcache_ctl_val |= MCACHE_CTL_IC_EN;
@@ -52,5 +55,9 @@ void harts_early_init(void)
                                while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
                        }
                }
+
+               mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+               csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
        }
 }

diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 12d5eb6f6c2e0f6804019ab9b5ff5d43df143c7e..3f3f05b348a0b781c080e95b5797c1d575a1dddb 100644 (file)
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -19,9 +19,15 @@
 #define MCACHE_CTL_IC_EN               BIT(0)
 #define MCACHE_CTL_DC_EN               BIT(1)
 #define MCACHE_CTL_CCTL_SUEN           BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN      BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN      BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN       BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN      BIT(15)
 #define MCACHE_CTL_DC_COHEN            BIT(19)
 #define MCACHE_CTL_DC_COHSTA           BIT(20)
 
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN      BIT(8)
 
 #define CCTL_L1D_WBINVAL_ALL 6