powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC

Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 4ef9be1b228e80389f33005c8f5dcc5caf0bf5bf..1aad2ba92557dbe4e32106390ad1d083cf44fbfd 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -166,12 +166,14 @@ int checkcpu (void)
        }
 #endif
 
+#if defined(CONFIG_FSL_LBC)
        if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
                printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
        } else {
                printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
                       sysinfo.freqLocalBus);
        }
+#endif
 
 #ifdef CONFIG_CPM2
        printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -284,7 +286,10 @@ void mpc85xx_reginfo(void)
 {
        print_tlbcam();
        print_laws();
+#if defined(CONFIG_FSL_LBC)
        print_lbc_regs();
+#endif
+
 }
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
@@ -330,8 +335,10 @@ phys_size_t initdram(int board_type)
        ddr_enable_ecc(dram_size);
 #endif
 
+#if defined(CONFIG_FSL_LBC)
        /* Some boards also have sdram on the lbc */
        lbc_sdram_init();
+#endif
 
        puts("DDR: ");
        return dram_size;

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3e9843ef07dbe5348e7dc2542674f09dcc..f2aa8d039d69053bb0d2517f2a6860575f927ce2 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
@@ -131,7 +131,9 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #else
        uint plat_ratio,e500_ratio,half_freqSystemBus;
+#if defined(CONFIG_FSL_LBC)
        uint lcrr_div;
+#endif
        int i;
 #ifdef CONFIG_QE
        u32 qe_ratio;
@@ -168,6 +170,7 @@ void get_sys_info (sys_info_t * sysInfo)
        sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
 
+#if defined(CONFIG_FSL_LBC)
 #if defined(CONFIG_SYS_LBC_LCRR)
        /* We will program LCRR to this value later */
        lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -193,6 +196,7 @@ void get_sys_info (sys_info_t * sysInfo)
                /* In case anyone cares what the unknown value is */
                sysInfo->freqLocalBus = lcrr_div;
        }
+#endif
 }