sunxi: mmc: Fix clk-delay settings

In recent allwinner kernel sources the mmc/sdio clk-delay settings have
been slightly tweaked, and for sun9i they are completely different then
what we are using.

This commit brings us in sync with what allwinner does, fixing problems
accessing sdcards on some A33 devices (and likely others).

For pre sun9i hardware this makes the following changes:
-At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk)
-At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk)
-Above 50 MHz change the out delay from 2 to 1 (first introduced in A20 sdk)

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 25f18adb67257359160803e92733a7ebaa938ac2..e717c44216297fba3583098fad6cb20da8c58d98 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -120,17 +120,27 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
        /* determine delays */
        if (hz <= 400000) {
                oclk_dly = 0;
-               sclk_dly = 7;
+               sclk_dly = 0;
        } else if (hz <= 25000000) {
                oclk_dly = 0;
                sclk_dly = 5;
+#ifdef CONFIG_MACH_SUN9I
        } else if (hz <= 50000000) {
-               oclk_dly = 3;
-               sclk_dly = 5;
+               oclk_dly = 5;
+               sclk_dly = 4;
        } else {
                /* hz > 50000000 */
                oclk_dly = 2;
                sclk_dly = 4;
+#else
+       } else if (hz <= 50000000) {
+               oclk_dly = 3;
+               sclk_dly = 4;
+       } else {
+               /* hz > 50000000 */
+               oclk_dly = 1;
+               sclk_dly = 4;
+#endif
        }
 
        writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |