clk: renesas: Synchronize R8A7790 H2 clock tables with Linux 6.5.3

Synchronize R-Car R8A7790 H2 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 1f3477fa6e5124990fe78e771dc25901bfd2570e..686f2af0052fb902e4a892e33d1f6a6b23fb1bd1 100644 (file)
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -38,7 +38,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7790_core_clks[] = {
+static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",     CLK_EXTAL),
        DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -88,7 +88,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] = {
        DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
 };
 
-static const struct mssr_mod_clk r8a7790_mod_clks[] = {
+static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
        DEF_MOD("msiof0",                  0,   R8A7790_CLK_MP),
        DEF_MOD("vcp1",                  100,   R8A7790_CLK_ZS),
        DEF_MOD("vcp0",                  101,   R8A7790_CLK_ZS),
@@ -230,7 +230,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 12) | \
                                         (((md) & BIT(13)) >> 12) | \
                                         (((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
        { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
        { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
 };