rockchip: rk3399: move SoC setting into arch_cpu_init()

SoC setting like DDR secure region and EMMC clock setting
should go to arch_cpu_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index b790ad909c9f4d9f33ab205344eafd1e33709b3a..2757c27da05c2642ee44265b7f5680f76a033b5e 100644 (file)
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -16,7 +16,6 @@
 #include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru_rk3399.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/periph.h>
 #include <asm/arch-rockchip/sys_proto.h>
@@ -65,11 +64,14 @@ __weak void rockchip_stimer_init(void)
 {
 }
 
+__weak int arch_cpu_init(void)
+{
+       return 0;
+}
+
 void board_init_f(ulong dummy)
 {
        struct udevice *dev;
-       struct rk3399_pmusgrf_regs *sgrf;
-       struct rk3399_grf_regs *grf;
        int ret;
 
 #ifdef CONFIG_DEBUG_UART
@@ -100,29 +102,14 @@ void board_init_f(ulong dummy)
        debug("U-Boot SPL board init\n");
 #endif
 
+       arch_cpu_init();
+
        ret = spl_early_init();
        if (ret) {
                debug("spl_early_init() failed: %d\n", ret);
                hang();
        }
 
-       /*
-        * Disable DDR and SRAM security regions.
-        *
-        * As we are entered from the BootROM, the region from
-        * 0x0 through 0xfffff (i.e. the first MB of memory) will
-        * be protected. This will cause issues with the DW_MMC
-        * driver, which tries to DMA from/to the stack (likely)
-        * located in this range.
-        */
-       sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
-       rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
-       rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
-
-       /*  eMMC clock generator: disable the clock multipilier */
-       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-       rk_clrreg(&grf->emmccore_con[11], 0x0ff);
-
        rockchip_stimer_init();
 
        ret = uclass_get_device(UCLASS_RAM, 0, &dev);

diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index dacbcf8fdf576c8fc1dcded60f14573790e1b97e..ead878b3fdcbf960812f8dde9cac4f16f50e3011 100644 (file)
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -80,11 +80,28 @@ int dram_init_banksize(void)
 
 int arch_cpu_init(void)
 {
-       /* We do some SoC one time setting here. */
-       struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
-       /* Emmc clock generator: disable the clock multipilier */
+#ifdef CONFIG_SPL_BUILD
+       struct rk3399_pmusgrf_regs *sgrf;
+       struct rk3399_grf_regs *grf;
+
+       /*
+        * Disable DDR and SRAM security regions.
+        *
+        * As we are entered from the BootROM, the region from
+        * 0x0 through 0xfffff (i.e. the first MB of memory) will
+        * be protected. This will cause issues with the DW_MMC
+        * driver, which tries to DMA from/to the stack (likely)
+        * located in this range.
+        */
+       sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
+       rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
+       rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
+
+       /*  eMMC clock generator: disable the clock multipilier */
+       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
        rk_clrreg(&grf->emmccore_con[11], 0x0ff);
+#endif
 
        return 0;
 }