powerpc/t4qds: cleanup board header file

CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index a397238e1aaec1b9632780ec9914a09afd418f3a..2006390335cc10e4c10adde9e6effb216ade40b6 100644 (file)
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -128,14 +128,9 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP                64      /* number of TLB1 entries */
-#endif
 
-#if 0
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY     /* test POST memory test */
-#endif
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END         0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
@@ -146,10 +141,8 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_SYS_INIT_L3_ADDR                CONFIG_RAMBOOT_TEXT_BASE
 
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR             0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS                0xf00000000ull
-#endif
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
@@ -187,11 +180,7 @@ unsigned long get_board_ddr_clk(void);
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE  0xe0000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS     (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
-#endif
 
 #define CONFIG_SYS_NOR0_CSPR_EXT       (0xf)
 #define CONFIG_SYS_NOR0_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
@@ -243,11 +232,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
-#ifdef CONFIG_PHYS_64BIT
 #define QIXIS_BASE_PHYS                (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS                QIXIS_BASE
-#endif
 
 #define CONFIG_SYS_CSPR3_EXT   (0xf)
 #define CONFIG_SYS_CSPR3       (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
@@ -270,11 +255,7 @@ unsigned long get_board_ddr_clk(void);
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE           0xff800000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
-#endif
 
 #define CONFIG_SYS_NAND_CSPR_EXT       (0xf)
 #define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -375,18 +356,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0xfdd00000      /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH     0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW      0xfe0ec000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
        ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
          CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS  0xfe0ec000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
 #define CONFIG_SYS_INIT_RAM_SIZE               0x00004000
 
 #define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
@@ -460,19 +435,11 @@ unsigned long get_board_ddr_clk(void);
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT      0xa0000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO1_MEM_PHYS      0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS      0xa0000000
-#endif
 #define CONFIG_SYS_SRIO1_MEM_SIZE      0x10000000      /* 256M */
 
 #define CONFIG_SYS_SRIO2_MEM_VIRT      0xb0000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO2_MEM_PHYS      0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS      0xb0000000
-#endif
 #define CONFIG_SYS_SRIO2_MEM_SIZE      0x10000000      /* 256M */
 
 /*
@@ -520,59 +487,32 @@ unsigned long get_board_ddr_clk(void);
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
-#endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
-#endif
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
-#endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
-#endif
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
-#endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
-#endif
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 4, Base address 203000 */
@@ -588,19 +528,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_DPAA_QBMAN          /* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS    50
 #define CONFIG_SYS_BMAN_MEM_BASE       0xf4000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_BMAN_MEM_PHYS       0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS       CONFIG_SYS_BMAN_MEM_BASE
-#endif
 #define CONFIG_SYS_BMAN_MEM_SIZE       0x02000000
 #define CONFIG_SYS_QMAN_NUM_PORTALS    50
 #define CONFIG_SYS_QMAN_MEM_BASE       0xf6000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_QMAN_MEM_PHYS       0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS       CONFIG_SYS_QMAN_MEM_BASE
-#endif
 #define CONFIG_SYS_QMAN_MEM_SIZE       0x02000000
 
 #define CONFIG_SYS_DPAA_FMAN