]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
armv8: layerscape: move TZASC and TZPC configs to Kconfig
authorRajesh Bhagat <rajesh.bhagat@nxp.com>
Sun, 20 Jan 2019 05:30:06 +0000 (05:30 +0000)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Tue, 19 Feb 2019 04:56:44 +0000 (10:26 +0530)
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/include/asm/arch-fsl-layerscape/config.h
include/configs/ls2080a_common.h
scripts/config_whitelist.txt

index a844b34b617a4664902d5ebaeed83f6e6fe23135..614b242f70ffa0c65bae44e572fc6f711137a324 100644 (file)
@@ -113,6 +113,8 @@ config ARCH_LS1088A
        select SYS_FSL_SRDS_1
        select SYS_FSL_SRDS_2
        select FSL_TZASC_1
+       select FSL_TZASC_400
+       select FSL_TZPC_BP147
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
@@ -145,6 +147,8 @@ config ARCH_LS2080A
        select SYS_FSL_SRDS_2
        select FSL_TZASC_1
        select FSL_TZASC_2
+       select FSL_TZASC_400
+       select FSL_TZPC_BP147
        select SYS_FSL_ERRATUM_A008336 if !TFABOOT
        select SYS_FSL_ERRATUM_A008511 if !TFABOOT
        select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@@ -410,6 +414,11 @@ config FSL_TZASC_1
 config FSL_TZASC_2
        bool
 
+config FSL_TZASC_400
+       bool
+
+config FSL_TZPC_BP147
+       bool
 endmenu
 
 menu "Layerscape clock tree configuration"
index d4f80a24cd713fff76ce5862e30df5bba87de1c0..903d5096c71829890db36635dbf7f7275d85b5e1 100644 (file)
@@ -26,7 +26,6 @@
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
-#define CONFIG_FSL_TZASC_400
 #endif
 
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS             3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1 }
 #define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
-#define CONFIG_FSL_TZASC_400
 #define CONFIG_SYS_PAGE_SIZE           0x10000
 
 #define        SRDS_MAX_LANES  4
index 235a757f75279bbe666c05d8a5c3a70627eeef90..bc6a6c1924bf438650c4207c2c19f9746a947db9 100644 (file)
@@ -10,7 +10,6 @@
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
 
 #include <asm/arch/stream_id_lsch3.h>
 #include <asm/arch/config.h>
index 2b3572568b1ccb8c9d253ee553665f01eeb709ca..ef4efd4d724c9436cb18f03f1c4f3c3199dae41f 100644 (file)
@@ -670,8 +670,6 @@ CONFIG_FSL_SGMII_RISER
 CONFIG_FSL_SPI_INTERFACE
 CONFIG_FSL_TBCLK_EXTRA_DIV
 CONFIG_FSL_TRUST_ARCH_v1
-CONFIG_FSL_TZASC_400
-CONFIG_FSL_TZPC_BP147
 CONFIG_FSL_USDHC
 CONFIG_FSL_VIA
 CONFIG_FSMC_NAND_BASE