EXYNOS: Clock: Add common function for pll rate calculation

Moved the common code to calculate pll clock rate to new function
exynos_get_pll_clk().

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 4f3b451be9955cc6e09047b5daedbe39ea2c412f..a0424238ae52408c6d67f156a489be006292ffbd 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,41 +26,19 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
-       struct exynos4_clock *clk =
-               (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned long r, m, p, s, k = 0, mask, fout;
+       unsigned long m, p, s = 0, mask, fout;
        unsigned int freq;
-
-       switch (pllreg) {
-       case APLL:
-               r = readl(&clk->apll_con0);
-               break;
-       case MPLL:
-               r = readl(&clk->mpll_con0);
-               break;
-       case EPLL:
-               r = readl(&clk->epll_con0);
-               k = readl(&clk->epll_con1);
-               break;
-       case VPLL:
-               r = readl(&clk->vpll_con0);
-               k = readl(&clk->vpll_con1);
-               break;
-       default:
-               printf("Unsupported PLL (%d)\n", pllreg);
-               return 0;
-       }
-
        /*
         * APLL_CON: MIDV [25:16]
         * MPLL_CON: MIDV [25:16]
         * EPLL_CON: MIDV [24:16]
         * VPLL_CON: MIDV [24:16]
+        * BPLL_CON: MIDV [25:16]: Exynos5
         */
-       if (pllreg == APLL || pllreg == MPLL)
+       if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
                mask = 0x3ff;
        else
                mask = 0x1ff;
@@ -92,13 +70,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
        return fout;
 }
 
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long r, k = 0;
+
+       switch (pllreg) {
+       case APLL:
+               r = readl(&clk->apll_con0);
+               break;
+       case MPLL:
+               r = readl(&clk->mpll_con0);
+               break;
+       case EPLL:
+               r = readl(&clk->epll_con0);
+               k = readl(&clk->epll_con1);
+               break;
+       case VPLL:
+               r = readl(&clk->vpll_con0);
+               k = readl(&clk->vpll_con1);
+               break;
+       default:
+               printf("Unsupported PLL (%d)\n", pllreg);
+               return 0;
+       }
+
+       return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos5: return pll clock frequency */
 static unsigned long exynos5_get_pll_clk(int pllreg)
 {
        struct exynos5_clock *clk =
                (struct exynos5_clock *)samsung_get_base_clock();
-       unsigned long r, m, p, s, k = 0, mask, fout;
-       unsigned int freq, pll_div2_sel, fout_sel;
+       unsigned long r, k = 0, fout;
+       unsigned int pll_div2_sel, fout_sel;
 
        switch (pllreg) {
        case APLL:
@@ -123,41 +131,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
                return 0;
        }
 
-       /*
-        * APLL_CON: MIDV [25:16]
-        * MPLL_CON: MIDV [25:16]
-        * EPLL_CON: MIDV [24:16]
-        * VPLL_CON: MIDV [24:16]
-        * BPLL_CON: MIDV [25:16]
-        */
-       if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
-               mask = 0x3ff;
-       else
-               mask = 0x1ff;
-
-       m = (r >> 16) & mask;
-
-       /* PDIV [13:8] */
-       p = (r >> 8) & 0x3f;
-       /* SDIV [2:0] */
-       s = r & 0x7;
-
-       freq = CONFIG_SYS_CLK_FREQ;
-
-       if (pllreg == EPLL) {
-               k = k & 0xffff;
-               /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 65536) * (freq / (p * (1 << s)));
-       } else if (pllreg == VPLL) {
-               k = k & 0xfff;
-               /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 1024) * (freq / (p * (1 << s)));
-       } else {
-               if (s < 1)
-                       s = 1;
-               /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-               fout = m * (freq / (p * (1 << (s - 1))));
-       }
+       fout = exynos_get_pll_clk(pllreg, r, k);
 
        /* According to the user manual, in EVT1 MPLL and BPLL always gives
         * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/