#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
+#define PCI_CFG_PIIX4_IDETIM_PRI 0x40
+#define PCI_CFG_PIIX4_IDETIM_SEC 0x42
+
+#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15)
+
#endif /* _MIPS_ASM_MALTA_H */
*/
#include <common.h>
+#include <ide.h>
#include <netdev.h>
#include <pci.h>
#include <pci_gt64120.h>
pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+
+ bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB, 0);
+ if (bdf == -1)
+ panic("Failed to find PIIX4 IDE controller\n");
+
+ /* enable bus master & IO access */
+ val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+ pci_write_config_dword(bdf, PCI_COMMAND, val32);
+
+ /* set latency */
+ pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
+
+ /* enable IDE/ATA */
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
+ PCI_CFG_PIIX4_IDETIM_IDE);
}
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+/*
+ * IDE/ATA
+ */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+
/*
* Commands
*/
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING