Nokia RX-51: Remove function set_muxconf_regs()

This function is not used and was never called.

This board contains '#define CONFIG_SKIP_LOWLEVEL_INIT' because X-Loader
set everything up, including MUX configuration.

Also this MUX configuration is incorrect and does not match hardware.

So remove this dead, unused and broken code.

This change will decrease size of U-Boot binary.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>

diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 1f508d5cda6510ecb2d1e5c7fdce34d8659d5bb5..d972e349114aa0476b10c2d1f687dc3677cf3a33 100644 (file)
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -468,17 +468,6 @@ int misc_init_r(void)
        return 0;
 }
 
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *             hardware. Many pins need to be moved from protect to primary
- *             mode.
- */
-void set_muxconf_regs(void)
-{
-       MUX_RX51();
-}
-
 static unsigned long int twl_wd_time; /* last time of watchdog reset */
 static unsigned long int twl_i2c_lock;
 

diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
index 4eff823a1b3c201d556874d3be0384fd05171716..0eddb062197fd0ff074f003d435315e9a012f8c4 100644 (file)
--- a/board/nokia/rx51/rx51.h
+++ b/board/nokia/rx51/rx51.h
@@ -21,352 +21,6 @@ struct emu_hal_params_rx51 {
        u32 param4;
 };
 
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_RX51() \
-/* SDRC */\
-       MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-       MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-       MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-       MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-       MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-       MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-       MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-       MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-       MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-       MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-       MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-       MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-       MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-       MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-       MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-       MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-       MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-       MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-       MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-       MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-       MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-       MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-       MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-       MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-       MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-       MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-       MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-       MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-       MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-       MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-       MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-       MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-       MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-       MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-       MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-       MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-       MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
-/* GPMC */\
-       MUX_VAL(CP(GPMC_A1),            (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-       MUX_VAL(CP(GPMC_A2),            (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-       MUX_VAL(CP(GPMC_A3),            (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-       MUX_VAL(CP(GPMC_A4),            (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-       MUX_VAL(CP(GPMC_A5),            (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-       MUX_VAL(CP(GPMC_A6),            (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-       MUX_VAL(CP(GPMC_A7),            (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-       MUX_VAL(CP(GPMC_A8),            (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-       MUX_VAL(CP(GPMC_A9),            (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-       MUX_VAL(CP(GPMC_A10),           (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
-       MUX_VAL(CP(GPMC_D0),            (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
-       MUX_VAL(CP(GPMC_D1),            (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
-       MUX_VAL(CP(GPMC_D2),            (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
-       MUX_VAL(CP(GPMC_D3),            (IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
-       MUX_VAL(CP(GPMC_D4),            (IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
-       MUX_VAL(CP(GPMC_D5),            (IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
-       MUX_VAL(CP(GPMC_D6),            (IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
-       MUX_VAL(CP(GPMC_D7),            (IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
-       MUX_VAL(CP(GPMC_D8),            (IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
-       MUX_VAL(CP(GPMC_D9),            (IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
-       MUX_VAL(CP(GPMC_D10),           (IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
-       MUX_VAL(CP(GPMC_D11),           (IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
-       MUX_VAL(CP(GPMC_D12),           (IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
-       MUX_VAL(CP(GPMC_D13),           (IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
-       MUX_VAL(CP(GPMC_D14),           (IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
-       MUX_VAL(CP(GPMC_D15),           (IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
-       MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-       MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-       MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
-       MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
-       MUX_VAL(CP(GPMC_NCS4),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
-       MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
-       MUX_VAL(CP(GPMC_NCS6),          (IEN  | PTD | DIS | M1)) /*nDMA_REQ2*/\
-       MUX_VAL(CP(GPMC_NCS7),          (IEN  | PTU | EN  | M1)) /*nDMA_REQ3*/\
-       MUX_VAL(CP(GPMC_NBE1),          (IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
-       MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
-       MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
-       MUX_VAL(CP(GPMC_CLK),           (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-       MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
-       MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-       MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-       MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
-       MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
-       MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-       MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
-/* DSS */\
-       MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-       MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-       MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-       MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-       MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-       MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-       MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-       MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-       MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-       MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-       MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-       MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-       MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-       MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-       MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-       MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-       MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-       MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-       MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-       MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-       MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-       MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-       MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-       MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-       MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-       MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-       MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-       MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-/* CAMERA */\
-       MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) /*CAM_HS*/\
-       MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) /*CAM_VS*/\
-       MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-       MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
-       MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-       MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
-       MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
-       MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
-       MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
-       MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
-       MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
-       MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
-       MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
-       MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
-       MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
-       MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
-       MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-       MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-       MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-       MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-       MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-       MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
-       MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
-       MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
-/* Audio Interface */\
-       MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
-       MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) /*McBSP2_CLK*/\
-       MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
-       MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-/* Expansion card */\
-       MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-       MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-       MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-       MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-       MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-       MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-       MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
-       MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
-       MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
-       MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
-/* Wireless LAN */\
-       MUX_VAL(CP(MMC2_CLK),           (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
-       MUX_VAL(CP(MMC2_CMD),           (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
-       MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
-       MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
-       MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
-       MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
-       MUX_VAL(CP(MMC2_DAT4),          (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
-       MUX_VAL(CP(MMC2_DAT5),          (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
-       MUX_VAL(CP(MMC2_DAT6),          (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
-       MUX_VAL(CP(MMC2_DAT7),          (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
-/* Bluetooth */\
-       MUX_VAL(CP(MCBSP3_DX),          (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
-       MUX_VAL(CP(MCBSP3_DR),          (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
-       MUX_VAL(CP(MCBSP3_CLKX),        (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
-       MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
-       MUX_VAL(CP(UART2_CTS),          (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
-       MUX_VAL(CP(UART2_RTS),          (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
-       MUX_VAL(CP(UART2_TX),           (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
-       MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
-/* Modem Interface */\
-       MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-       MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
-       MUX_VAL(CP(UART1_CTS),          (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
-       MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
-       MUX_VAL(CP(MCBSP4_CLKX),        (IEN  | PTD | DIS | M1)) /*SSI1_DAT*/\
-       MUX_VAL(CP(MCBSP4_DR),          (IEN  | PTD | DIS | M1)) /*SSI1_FLAG*/\
-       MUX_VAL(CP(MCBSP4_DX),          (IEN  | PTD | DIS | M1)) /*SSI1_RDY*/\
-       MUX_VAL(CP(MCBSP4_FSX),         (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
-       MUX_VAL(CP(MCBSP1_CLKR),        (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-       MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M4)) /*GPIO_157*/\
-       MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
-       MUX_VAL(CP(MCBSP1_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-       MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
-       MUX_VAL(CP(MCBSP1_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
-       MUX_VAL(CP(MCBSP1_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
-/* Serial Interface */\
-       MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTD | EN  | M0)) /*UART3_CTS*/\
-       MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
-       MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) /*UART3_RX*/\
-       MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
-       MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-       MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-       MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-       MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-       MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA0*/\
-       MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA1*/\
-       MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA2*/\
-       MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA3*/\
-       MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA4*/\
-       MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA5*/\
-       MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA6*/\
-       MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DA7*/\
-       MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
-       MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
-       MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M4)) /*GPIO_168*/\
-       MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
-       MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
-       MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
-       MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
-       MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-       MUX_VAL(CP(HDQ_SIO),            (IDIS | PTU | EN  | M4)) /*GPIO_170*/\
-       MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTU | EN  | M4)) /*GPIO_171*/\
-       MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTU | EN  | M4)) /*GPIO_172*/\
-       MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) /*McSPI1_SOM*/\
-       MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
-       MUX_VAL(CP(MCSPI1_CS1),         (IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
-       MUX_VAL(CP(MCSPI1_CS2),         (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
-/* USB EHCI (port 2) */\
-       MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTU | DIS | M3)) /*HSUSB2_DA2*/\
-       MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTU | DIS | M3)) /*HSUSB2_DA7*/\
-       MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DA4*/\
-       MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DA5*/\
-       MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTU | DIS | M3)) /*HSUSB2_DA6*/\
-       MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTU | DIS | M3)) /*HSUSB2_DA3*/\
-       MUX_VAL(CP(ETK_D10_ES2),        (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
-       MUX_VAL(CP(ETK_D11_ES2),        (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
-       MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
-       MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
-       MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DA0*/\
-       MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DA1*/\
-/* Control and debug */\
-       MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-       MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-       MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-       MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-       MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
-       MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*MMC1_WP*/\
-       MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-       MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-       MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-       MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
-       MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)) /*SYS_OFF_MD*/\
-       MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT*/\
-       MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
-       MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
-       MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
-       MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA0*/\
-       MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA1*/\
-       MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA2*/\
-       MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA7*/\
-       MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA4*/\
-       MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA5*/\
-       MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA6*/\
-       MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DA3*/\
-       MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
-       MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
-       MUX_VAL(CP(D2D_MCAD1),          (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-       MUX_VAL(CP(D2D_MCAD2),          (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-       MUX_VAL(CP(D2D_MCAD3),          (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-       MUX_VAL(CP(D2D_MCAD4),          (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-       MUX_VAL(CP(D2D_MCAD5),          (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-       MUX_VAL(CP(D2D_MCAD6),          (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-       MUX_VAL(CP(D2D_MCAD7),          (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-       MUX_VAL(CP(D2D_MCAD8),          (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-       MUX_VAL(CP(D2D_MCAD9),          (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-       MUX_VAL(CP(D2D_MCAD10),         (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-       MUX_VAL(CP(D2D_MCAD11),         (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-       MUX_VAL(CP(D2D_MCAD12),         (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-       MUX_VAL(CP(D2D_MCAD13),         (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-       MUX_VAL(CP(D2D_MCAD14),         (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-       MUX_VAL(CP(D2D_MCAD15),         (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-       MUX_VAL(CP(D2D_MCAD16),         (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-       MUX_VAL(CP(D2D_MCAD17),         (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-       MUX_VAL(CP(D2D_MCAD18),         (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-       MUX_VAL(CP(D2D_MCAD19),         (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-       MUX_VAL(CP(D2D_MCAD20),         (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-       MUX_VAL(CP(D2D_MCAD21),         (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-       MUX_VAL(CP(D2D_MCAD22),         (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-       MUX_VAL(CP(D2D_MCAD23),         (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-       MUX_VAL(CP(D2D_MCAD24),         (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-       MUX_VAL(CP(D2D_MCAD25),         (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-       MUX_VAL(CP(D2D_MCAD26),         (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-       MUX_VAL(CP(D2D_MCAD27),         (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-       MUX_VAL(CP(D2D_MCAD28),         (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-       MUX_VAL(CP(D2D_MCAD29),         (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-       MUX_VAL(CP(D2D_MCAD30),         (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-       MUX_VAL(CP(D2D_MCAD31),         (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-       MUX_VAL(CP(D2D_MCAD32),         (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-       MUX_VAL(CP(D2D_MCAD33),         (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-       MUX_VAL(CP(D2D_MCAD34),         (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-       MUX_VAL(CP(D2D_MCAD35),         (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-       MUX_VAL(CP(D2D_MCAD36),         (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-       MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0)) /*d2d_clk26m*/\
-       MUX_VAL(CP(D2D_NRESPWRON),      (IEN  | PTD | EN  | M0)) /*d2d_nrespw*/\
-       MUX_VAL(CP(D2D_NRESWARM),       (IEN  | PTU | EN  | M0)) /*d2d_nreswa*/\
-       MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0)) /*d2d_arm9ni*/\
-       MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0)) /*d2d_uma2p6*/\
-       MUX_VAL(CP(D2D_SPINT),          (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-       MUX_VAL(CP(D2D_FRINT),          (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-       MUX_VAL(CP(D2D_DMAREQ0),        (IEN  | PTD | DIS | M0)) /*d2d_dmare0*/\
-       MUX_VAL(CP(D2D_DMAREQ1),        (IEN  | PTD | DIS | M0)) /*d2d_dmare1*/\
-       MUX_VAL(CP(D2D_DMAREQ2),        (IEN  | PTD | DIS | M0)) /*d2d_dmare2*/\
-       MUX_VAL(CP(D2D_DMAREQ3),        (IEN  | PTD | DIS | M0)) /*d2d_dmare3*/\
-       MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtrs*/\
-       MUX_VAL(CP(D2D_N3GTDI),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-       MUX_VAL(CP(D2D_N3GTDO),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-       MUX_VAL(CP(D2D_N3GTMS),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-       MUX_VAL(CP(D2D_N3GTCK),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-       MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0)) /*d2d_n3grtc*/\
-       MUX_VAL(CP(D2D_MSTDBY),         (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-       MUX_VAL(CP(D2D_SWAKEUP),        (IEN  | PTD | EN  | M0)) /*d2d_swakeu*/\
-       MUX_VAL(CP(D2D_IDLEREQ),        (IEN  | PTD | DIS | M0)) /*d2d_idlere*/\
-       MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0)) /*d2d_idleac*/\
-       MUX_VAL(CP(D2D_MWRITE),         (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-       MUX_VAL(CP(D2D_SWRITE),         (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-       MUX_VAL(CP(D2D_MREAD),          (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-       MUX_VAL(CP(D2D_SREAD),          (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-       MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0)) /*d2d_mbusfl*/\
-       MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0)) /*d2d_sbusfl*/\
-       MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-       MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
-
-#define MUX_RX51_C() \
-       MUX_VAL(CP(MCBSP3_DX),          (IEN | PTD | DIS | M4)) /*GPIO_140*/\
-       MUX_VAL(CP(MCBSP3_DR),          (IEN | PTD | DIS | M4)) /*GPIO_142*/\
-       MUX_VAL(CP(MCBSP3_CLKX),        (IEN | PTD | DIS | M4)) /*GPIO_141*/\
-       MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
-       MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
-       MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) /*UART2_TX*/
-
 #define ONENAND_GPMC_CONFIG1_RX51      0xfb001202
 #define ONENAND_GPMC_CONFIG2_RX51      0x00111100
 #define ONENAND_GPMC_CONFIG3_RX51      0x00020200