ppc4xx: DDR/ECC: Use correct macros to clear error status

Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.

Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c
index f105605459d5aec6490d70dccc111e8633e23968..49f28d93e0e07f3adffba2ec30c6e18821f1bbb0 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/ecc.c
+++ b/arch/powerpc/cpu/ppc4xx/ecc.c
@@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address,
 
                /* clear ECC error repoting registers */
                mtsdram(SDRAM_ECCES, 0xffffffff);
-               mtdcr(0x4c, 0xffffffff);
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+               /*
+                * IBM DDR(1) core (440GX):
+                * Clear Mx bits in SDRAM0_BESR0/1
+                */
+               mtsdram(SDRAM0_BESR0, 0xffffffff);
+               mtsdram(SDRAM0_BESR1, 0xffffffff);
+#elif defined(CONFIG_440)
+               /*
+                * 440/460 DDR2 core:
+                * Clear EMID (Error PLB Master ID) in MQ0_ESL
+                */
+               mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
+#else
+               /*
+                * 405EX(r) DDR2 core:
+                * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
+                */
+               mtsdram(SDRAM_BESR, 0xf0000000);
+#endif
 
                mtsdram(SDRAM_MCOPT1,
                        (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);

diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 42eac4531f429b7c7ac894f2a46ac022e6eb5f96..4ec1ef866a4b5f26ec19620e2abaac4b7854fb3c 100644 (file)
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -63,6 +63,8 @@
 #define SDRAM_CFG0     0x20    /* memory controller options 0          */
 #define SDRAM_CFG1     0x21    /* memory controller options 1          */
 
+#define SDRAM0_BESR0   0x0000  /* bus error status reg 0               */
+#define SDRAM0_BESR1   0x0008  /* bus error status reg 1               */
 #define SDRAM0_BEAR    0x0010  /* bus error address reg                */
 #define SDRAM0_SLIO    0x0018  /* ddr sdram slave interface options    */
 #define SDRAM0_CFG0    0x0020  /* ddr sdram options 0                  */