]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
armv8/fsl-lsch3: Add support for second DDR clock
authorYork Sun <yorksun@freescale.com>
Tue, 6 Jan 2015 21:18:49 +0000 (13:18 -0800)
committerYork Sun <yorksun@freescale.com>
Tue, 24 Feb 2015 21:09:14 +0000 (13:09 -0800)
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.

Signed-off-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv8/fsl-lsch3/cpu.c
arch/arm/cpu/armv8/fsl-lsch3/speed.c
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
arch/arm/include/asm/global_data.h

index 2aaac017d2655c5419080ae816fdac7c9c71d08e..42cee65546232246101e0ffff9ef59a33ed5aba1 100644 (file)
@@ -367,6 +367,7 @@ int print_cpuinfo(void)
        printf("\n       Bus:      %-4s MHz  ",
               strmhz(buf, sysinfo.freq_systembus));
        printf("DDR:      %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
+       printf("     DP-DDR:   %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
        puts("\n");
 
        return 0;
index dc4a34bce5c37d5f4264a77717a1c09656bae5be..72cd999c5fd0e2e35594eef7a5f33e3d4729e311 100644 (file)
@@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
        sys_info->freq_systembus = sysclk;
 #ifdef CONFIG_DDR_CLK_FREQ
        sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+       sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
 #else
        sys_info->freq_ddrbus = sysclk;
+       sys_info->freq_ddrbus2 = sysclk;
 #endif
 
        sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
@@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
        sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
                        FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
                        FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+       sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+                       FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
+                       FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
 
        for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
                /*
@@ -129,7 +134,7 @@ int get_clocks(void)
        gd->cpu_clk = sys_info.freq_processor[0];
        gd->bus_clk = sys_info.freq_systembus;
        gd->mem_clk = sys_info.freq_ddrbus;
-
+       gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 #if defined(CONFIG_FSL_ESDHC)
        gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif /* defined(CONFIG_FSL_ESDHC) */
@@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
  * get_ddr_freq
  * return ddr bus freq in Hz
  *********************************************/
-ulong get_ddr_freq(ulong dummy)
+ulong get_ddr_freq(ulong ctrl_num)
 {
        if (!gd->mem_clk)
                get_clocks();
 
+       /*
+        * DDR controller 0 & 1 are on memory complex 0
+        * DDR controler 2 is on memory complext 1
+        */
+       if (ctrl_num >= 2)
+               return gd->arch.mem2_clk;
+
        return gd->mem_clk;
 }
 
index ee1d6512d90056686775cb07368c465f30ee4088..dd11ef79c8c2f2f97a38f35d98b9f4d9f07050a1 100644 (file)
@@ -15,6 +15,7 @@ struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
        unsigned long freq_systembus;
        unsigned long freq_ddrbus;
+       unsigned long freq_ddrbus2;
        unsigned long freq_localbus;
        unsigned long freq_qe;
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -60,6 +61,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK   0x1f
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT  10
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK   0x3f
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK  0x3f
        u8      res_180[0x200-0x180];
        u32     scratchrw[32];  /* Scratch Read/Write */
        u8      res_280[0x300-0x280];
index 438f128326a67a6c5237df32a0f392efdabee1c7..bb24f33d0d8816c089ba344d332ae40ed8c7002b 100644 (file)
@@ -48,6 +48,9 @@ struct arch_global_data {
 #ifdef CONFIG_OMAP
        struct omap_boot_parameters omap_boot_params;
 #endif
+#ifdef CONFIG_FSL_LSCH3
+       unsigned long mem2_clk;
+#endif
 };
 
 #include <asm-generic/global_data.h>