nand: Try to align the default buffers

The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index bfd668fa0ac5425f21361971ca5f0efc26bff4f7..891af1f2ea4a06b10a49837757997d5a16423532 100644 (file)
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
        struct nand_chip *chip = mtd->priv;
 
        if (!(chip->options & NAND_OWN_BUFFERS))
-               chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+               chip->buffers = memalign(ARCH_DMA_MINALIGN,
+                                        sizeof(*chip->buffers));
        if (!chip->buffers)
                return -ENOMEM;
 

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 82704de0835561907e5d77467c7c27458890f2e4..dc839e7153894e300084006b2260e116f01fb03a 100644 (file)
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
  * consecutive order.
  */
 struct nand_buffers {
-       uint8_t ecccalc[NAND_MAX_OOBSIZE];
-       uint8_t ecccode[NAND_MAX_OOBSIZE];
-       uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+       uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+       uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+       uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+                             ARCH_DMA_MINALIGN)];
 };
 
 /**