ARM: Introduce erratum workaround for 454179

454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index e918af73f9417f5343de7b01294a186648f37dc0..c3226386cfdb70a1223c4d431f8c96e61a22fadf 100644 (file)
--- a/README
+++ b/README
@@ -693,6 +693,7 @@ The following options need to be configured:
                NOTE: The following can be machine specific errata. These
                do have ability to provide rudimentary version and machine
                specific checks, but expect no product checks.
+               CONFIG_ARM_ERRATA_454179
                CONFIG_ARM_ERRATA_798870
 
 - Tegra SoC options:

diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c
index 8ac81c9ba147453be1705af4fa9cc813d6efce1a..b44c9f94a8222c07a5e46caf1cd9471aca46bcdb 100644 (file)
--- a/arch/arm/cpu/armv7/cp15.c
+++ b/arch/arm/cpu/armv7/cp15.c
@@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
 {
        asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
 }
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+                                u32 cpu_variant, u32 cpu_rev)
+{
+       asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
+}

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 89637e26395d86944bc06a1a2cf3a9a8217d4620..8483687879ed70054deb33cc4f56e22780ac1544 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -187,6 +187,19 @@ ENTRY(cpu_init_cp15)
        isb                             @ Recommended ISB after l2actlr update
        pop     {r1-r5}                 @ Restore the cpu info - fall through
 skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_454179
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x3 << 6)     @ Set DBSM(BIT7) and IBE(BIT6) bits
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_454179:
 #endif
 
        mov     pc, r5                  @ back to my caller

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index cd4091208c4565f79b2ccad64443366a33cbe47a..58d8b161215a6229fb0e9661a0687a49440ed70a 100644 (file)
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -140,6 +140,8 @@ extern char __secure_end[];
 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
                                 u32 cpu_rev_comb, u32 cpu_variant,
                                 u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+                         u32 cpu_variant, u32 cpu_rev);
 #endif /* ! __ASSEMBLY__ */
 
 #endif