Fix bug in [id]cache_status commands for MPC85xx processors;

should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005

diff --git a/CHANGELOG b/CHANGELOG
index 51efb237fbd38f51971c4b03460523d4ae2578ca..ac984168d4abb340cf709bade3948d229037ba69 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+  should look at LSB of L1CSRn registers to determine if L1 cache is
+  enabled, not the MSB.
+  Patch by Murray Jensen, 19 Jul 2005
+
 * Fix array overflow with fw_setenv on uninitialised environment
   Patch by Murray Jensen, 15 Jul 2005
 

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7ac65736bc03f697863ea7a058ed151ec8c59fbe..f96a4c3f8b0dcd2d0cf9ef2ebb719b50fbbadb98 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -715,7 +715,7 @@ icache_disable:
        .globl  icache_status
 icache_status:
        mfspr   r3,L1CSR1
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl  dcache_enable
@@ -748,7 +748,7 @@ dcache_disable:
        .globl  dcache_status
 dcache_status:
        mfspr   r3,L1CSR0
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl get_pir