arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
index 30c4d7d02a4e5e6855ffc7fe857a7c663906d092..ff64f555c06084890b94961568f986f0b2ed0a78 100644 (file)
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0