powerpc/srio: Update the SRIO LIODN registers and ID table macro

For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 3f543d9249154772e10aed27b95b4a0cd0d7889f..44bc88dcecd0ddd8cc20e1b8614888080050ce27 100644 (file)
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -29,6 +29,13 @@ struct srio_liodn_id_table {
                + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
        }
 
+#define SET_SRIO_LIODN_BASE(port, id_a) \
+       { .id = { id_a }, .num_ids = 1, .portid = port, \
+         .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+               + (port - 1) * 0x200 \
+               + CONFIG_SYS_FSL_SRIO_ADDR, \
+       }
+
 struct liodn_id_table {
        const char * compat;
        u32 id[2];

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 81b3322fe6dba842fb734461c1151e0eb19cfae9..90976809427bbbbfcb2a50971baa35873b557dc2 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1544,6 +1544,18 @@ struct rio_pw {
 };
 #endif
 
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+struct rio_liodn {
+       u32     plbr;
+       u8      res0[28];
+       u32     plaor;
+       u8      res1[12];
+       u32     pludr;
+       u32     plldr;
+       u8      res2[456];
+};
+#endif
+
 /* RapidIO Registers */
 struct ccsr_rio {
        struct rio_arch arch;
@@ -1566,6 +1578,10 @@ struct ccsr_rio {
        u8      res7[100];
        struct rio_pw   pw;
 #endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+       u8      res5[8192];
+       struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+#endif
 };
 #endif