fsl: Create common fsl_dma.h for 85xx and 86xx cpus

Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 9ad118842be9d2582aa3243b2f0c20f4fa3e3f76..331fcc09a4c1392023882d23a611343dae56f097 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -266,26 +266,28 @@ reset_85xx_watchdog(void)
 
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void) {
-       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+       volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-       dma->satr0 = 0x02c40000;
-       dma->datr0 = 0x02c40000;
-       dma->sr0 = 0xfffffff; /* clear any errors */
+       dma->satr = 0x02c40000;
+       dma->datr = 0x02c40000;
+       dma->sr = 0xfffffff; /* clear any errors */
        asm("sync; isync; msync");
        return;
 }
 
 uint dma_check(void) {
-       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-       volatile uint status = dma->sr0;
+       volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+       volatile fsl_dma_t *dma = &dma_base->dma[0];
+       volatile uint status = dma->sr;
 
        /* While the channel is busy, spin */
        while((status & 4) == 4) {
-               status = dma->sr0;
+               status = dma->sr;
        }
 
        /* clear MR0[CS] channel start bit */
-       dma->mr0 &= 0x00000001;
+       dma->mr &= 0x00000001;
        asm("sync;isync;msync");
 
        if (status != 0) {
@@ -295,14 +297,15 @@ uint dma_check(void) {
 }
 
 int dma_xfer(void *dest, uint count, void *src) {
-       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+       volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-       dma->dar0 = (uint) dest;
-       dma->sar0 = (uint) src;
-       dma->bcr0 = count;
-       dma->mr0 = 0xf000004;
+       dma->dar = (uint) dest;
+       dma->sar = (uint) src;
+       dma->bcr = count;
+       dma->mr = 0xf000004;
        asm("sync;isync;msync");
-       dma->mr0 = 0xf000005;
+       dma->mr = 0xf000005;
        asm("sync;isync;msync");
        return dma_check();
 }

diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 653a137396abf34d5dcd0351d67dfc7c5d25bca8..f35323ac67607bb11d4079694cf1c4f8b9e23dbf 100644 (file)
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -183,10 +183,11 @@ void
 dma_init(void)
 {
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile ccsr_dma_t *dma = &immap->im_dma;
+       volatile ccsr_dma_t *dma_base = &immap->im_dma;
+       volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-       dma->satr0 = 0x00040000;
-       dma->datr0 = 0x00040000;
+       dma->satr = 0x00040000;
+       dma->datr = 0x00040000;
        asm("sync; isync");
 }
 
@@ -194,12 +195,13 @@ uint
 dma_check(void)
 {
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile ccsr_dma_t *dma = &immap->im_dma;
-       volatile uint status = dma->sr0;
+       volatile ccsr_dma_t *dma_base = &immap->im_dma;
+       volatile fsl_dma_t *dma = &dma_base->dma[0];
+       volatile uint status = dma->sr;
 
        /* While the channel is busy, spin */
        while ((status & 4) == 4) {
-               status = dma->sr0;
+               status = dma->sr;
        }
 
        if (status != 0) {
@@ -212,14 +214,15 @@ int
 dma_xfer(void *dest, uint count, void *src)
 {
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile ccsr_dma_t *dma = &immap->im_dma;
+       volatile ccsr_dma_t *dma_base = &immap->im_dma;
+       volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-       dma->dar0 = (uint) dest;
-       dma->sar0 = (uint) src;
-       dma->bcr0 = count;
-       dma->mr0 = 0xf000004;
+       dma->dar = (uint) dest;
+       dma->sar = (uint) src;
+       dma->bcr = count;
+       dma->mr = 0xf000004;
        asm("sync;isync");
-       dma->mr0 = 0xf000005;
+       dma->mr = 0xf000005;
        asm("sync;isync");
        return dma_check();
 }

diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
new file mode 100644 (file)
index 0000000..aab8720
--- /dev/null
+++ b/include/asm-ppc/fsl_dma.h
@@ -0,0 +1,51 @@
+/*
+ * Freescale DMA Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_DMA_H_
+#define _ASM_FSL_DMA_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_dma {
+       uint    mr;             /* DMA mode register */
+       uint    sr;             /* DMA status register */
+       char    res0[4];
+       uint    clndar;         /* DMA current link descriptor address register */
+       uint    satr;           /* DMA source attributes register */
+       uint    sar;            /* DMA source address register */
+       uint    datr;           /* DMA destination attributes register */
+       uint    dar;            /* DMA destination address register */
+       uint    bcr;            /* DMA byte count register */
+       char    res1[4];
+       uint    nlndar;         /* DMA next link descriptor address register */
+       char    res2[8];
+       uint    clabdar;        /* DMA current List - alternate base descriptor address Register */
+       char    res3[4];
+       uint    nlsdar;         /* DMA next list descriptor address register */
+       uint    ssr;            /* DMA source stride register */
+       uint    dsr;            /* DMA destination stride register */
+       char    res4[56];
+} fsl_dma_t;
+
+#endif /* _ASM_DMA_H_ */

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0f9f493d1f39a09b17b4bc536e0086defef6515b..e4f5ee2bc9e9ef782d6b5292878f128218eaea23 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -12,6 +12,7 @@
 #define __IMMAP_85xx__
 
 #include <asm/types.h>
+#include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 #include <asm/fsl_lbc.h>
 
@@ -406,80 +407,9 @@ typedef struct ccsr_l2cache {
  */
 typedef struct ccsr_dma {
        char    res1[256];
-       uint    mr0;            /* 0x21100 - DMA 0 Mode Register */
-       uint    sr0;            /* 0x21104 - DMA 0 Status Register */
-       char    res2[4];
-       uint    clndar0;        /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
-       uint    satr0;          /* 0x21110 - DMA 0 Source Attributes Register */
-       uint    sar0;           /* 0x21114 - DMA 0 Source Address Register */
-       uint    datr0;          /* 0x21118 - DMA 0 Destination Attributes Register */
-       uint    dar0;           /* 0x2111c - DMA 0 Destination Address Register */
-       uint    bcr0;           /* 0x21120 - DMA 0 Byte Count Register */
-       char    res3[4];
-       uint    nlndar0;        /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
-       char    res4[8];
-       uint    clabdar0;       /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
-       char    res5[4];
-       uint    nlsdar0;        /* 0x2113c - DMA 0 Next List Descriptor Address Register */
-       uint    ssr0;           /* 0x21140 - DMA 0 Source Stride Register */
-       uint    dsr0;           /* 0x21144 - DMA 0 Destination Stride Register */
-       char    res6[56];
-       uint    mr1;            /* 0x21180 - DMA 1 Mode Register */
-       uint    sr1;            /* 0x21184 - DMA 1 Status Register */
-       char    res7[4];
-       uint    clndar1;        /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
-       uint    satr1;          /* 0x21190 - DMA 1 Source Attributes Register */
-       uint    sar1;           /* 0x21194 - DMA 1 Source Address Register */
-       uint    datr1;          /* 0x21198 - DMA 1 Destination Attributes Register */
-       uint    dar1;           /* 0x2119c - DMA 1 Destination Address Register */
-       uint    bcr1;           /* 0x211a0 - DMA 1 Byte Count Register */
-       char    res8[4];
-       uint    nlndar1;        /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
-       char    res9[8];
-       uint    clabdar1;       /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
-       char    res10[4];
-       uint    nlsdar1;        /* 0x211bc - DMA 1 Next List Descriptor Address Register */
-       uint    ssr1;           /* 0x211c0 - DMA 1 Source Stride Register */
-       uint    dsr1;           /* 0x211c4 - DMA 1 Destination Stride Register */
-       char    res11[56];
-       uint    mr2;            /* 0x21200 - DMA 2 Mode Register */
-       uint    sr2;            /* 0x21204 - DMA 2 Status Register */
-       char    res12[4];
-       uint    clndar2;        /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
-       uint    satr2;          /* 0x21210 - DMA 2 Source Attributes Register */
-       uint    sar2;           /* 0x21214 - DMA 2 Source Address Register */
-       uint    datr2;          /* 0x21218 - DMA 2 Destination Attributes Register */
-       uint    dar2;           /* 0x2121c - DMA 2 Destination Address Register */
-       uint    bcr2;           /* 0x21220 - DMA 2 Byte Count Register */
-       char    res13[4];
-       uint    nlndar2;        /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
-       char    res14[8];
-       uint    clabdar2;       /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
-       char    res15[4];
-       uint    nlsdar2;        /* 0x2123c - DMA 2 Next List Descriptor Address Register */
-       uint    ssr2;           /* 0x21240 - DMA 2 Source Stride Register */
-       uint    dsr2;           /* 0x21244 - DMA 2 Destination Stride Register */
-       char    res16[56];
-       uint    mr3;            /* 0x21280 - DMA 3 Mode Register */
-       uint    sr3;            /* 0x21284 - DMA 3 Status Register */
-       char    res17[4];
-       uint    clndar3;        /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
-       uint    satr3;          /* 0x21290 - DMA 3 Source Attributes Register */
-       uint    sar3;           /* 0x21294 - DMA 3 Source Address Register */
-       uint    datr3;          /* 0x21298 - DMA 3 Destination Attributes Register */
-       uint    dar3;           /* 0x2129c - DMA 3 Destination Address Register */
-       uint    bcr3;           /* 0x212a0 - DMA 3 Byte Count Register */
-       char    res18[4];
-       uint    nlndar3;        /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
-       char    res19[8];
-       uint    clabdar3;       /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
-       char    res20[4];
-       uint    nlsdar3;        /* 0x212bc - DMA 3 Next List Descriptor Address Register */
-       uint    ssr3;           /* 0x212c0 - DMA 3 Source Stride Register */
-       uint    dsr3;           /* 0x212c4 - DMA 3 Destination Stride Register */
-       char    res21[56];
+       struct fsl_dma dma[4];
        uint    dgsr;           /* 0x21300 - DMA General Status Register */
-       char    res22[11516];
+       char    res2[11516];
 } ccsr_dma_t;
 
 /*

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 470385ffd2f486a565f43aee00e1c84a6fb9ec75..689c720452b05a182144c5da93127b191568bccb 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -11,6 +11,7 @@
 #define __IMMAP_86xx__
 
 #include <asm/types.h>
+#include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 
 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
@@ -386,80 +387,9 @@ typedef struct ccsr_ht {
 /* DMA Registers(0x2_1000-0x2_2000) */
 typedef struct ccsr_dma {
        char    res1[256];
-       uint    mr0;            /* 0x21100 - DMA 0 Mode Register */
-       uint    sr0;            /* 0x21104 - DMA 0 Status Register */
-       char    res2[4];
-       uint    clndar0;        /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
-       uint    satr0;          /* 0x21110 - DMA 0 Source Attributes Register */
-       uint    sar0;           /* 0x21114 - DMA 0 Source Address Register */
-       uint    datr0;          /* 0x21118 - DMA 0 Destination Attributes Register */
-       uint    dar0;           /* 0x2111c - DMA 0 Destination Address Register */
-       uint    bcr0;           /* 0x21120 - DMA 0 Byte Count Register */
-       char    res3[4];
-       uint    nlndar0;        /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
-       char    res4[8];
-       uint    clabdar0;       /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
-       char    res5[4];
-       uint    nlsdar0;        /* 0x2113c - DMA 0 Next List Descriptor Address Register */
-       uint    ssr0;           /* 0x21140 - DMA 0 Source Stride Register */
-       uint    dsr0;           /* 0x21144 - DMA 0 Destination Stride Register */
-       char    res6[56];
-       uint    mr1;            /* 0x21180 - DMA 1 Mode Register */
-       uint    sr1;            /* 0x21184 - DMA 1 Status Register */
-       char    res7[4];
-       uint    clndar1;        /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
-       uint    satr1;          /* 0x21190 - DMA 1 Source Attributes Register */
-       uint    sar1;           /* 0x21194 - DMA 1 Source Address Register */
-       uint    datr1;          /* 0x21198 - DMA 1 Destination Attributes Register */
-       uint    dar1;           /* 0x2119c - DMA 1 Destination Address Register */
-       uint    bcr1;           /* 0x211a0 - DMA 1 Byte Count Register */
-       char    res8[4];
-       uint    nlndar1;        /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
-       char    res9[8];
-       uint    clabdar1;       /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
-       char    res10[4];
-       uint    nlsdar1;        /* 0x211bc - DMA 1 Next List Descriptor Address Register */
-       uint    ssr1;           /* 0x211c0 - DMA 1 Source Stride Register */
-       uint    dsr1;           /* 0x211c4 - DMA 1 Destination Stride Register */
-       char    res11[56];
-       uint    mr2;            /* 0x21200 - DMA 2 Mode Register */
-       uint    sr2;            /* 0x21204 - DMA 2 Status Register */
-       char    res12[4];
-       uint    clndar2;        /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
-       uint    satr2;          /* 0x21210 - DMA 2 Source Attributes Register */
-       uint    sar2;           /* 0x21214 - DMA 2 Source Address Register */
-       uint    datr2;          /* 0x21218 - DMA 2 Destination Attributes Register */
-       uint    dar2;           /* 0x2121c - DMA 2 Destination Address Register */
-       uint    bcr2;           /* 0x21220 - DMA 2 Byte Count Register */
-       char    res13[4];
-       uint    nlndar2;        /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
-       char    res14[8];
-       uint    clabdar2;       /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
-       char    res15[4];
-       uint    nlsdar2;        /* 0x2123c - DMA 2 Next List Descriptor Address Register */
-       uint    ssr2;           /* 0x21240 - DMA 2 Source Stride Register */
-       uint    dsr2;           /* 0x21244 - DMA 2 Destination Stride Register */
-       char    res16[56];
-       uint    mr3;            /* 0x21280 - DMA 3 Mode Register */
-       uint    sr3;            /* 0x21284 - DMA 3 Status Register */
-       char    res17[4];
-       uint    clndar3;        /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
-       uint    satr3;          /* 0x21290 - DMA 3 Source Attributes Register */
-       uint    sar3;           /* 0x21294 - DMA 3 Source Address Register */
-       uint    datr3;          /* 0x21298 - DMA 3 Destination Attributes Register */
-       uint    dar3;           /* 0x2129c - DMA 3 Destination Address Register */
-       uint    bcr3;           /* 0x212a0 - DMA 3 Byte Count Register */
-       char    res18[4];
-       uint    nlndar3;        /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
-       char    res19[8];
-       uint    clabdar3;       /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
-       char    res20[4];
-       uint    nlsdar3;        /* 0x212bc - DMA 3 Next List Descriptor Address Register */
-       uint    ssr3;           /* 0x212c0 - DMA 3 Source Stride Register */
-       uint    dsr3;           /* 0x212c4 - DMA 3 Destination Stride Register */
-       char    res21[56];
+       struct fsl_dma dma[4];
        uint    dgsr;           /* 0x21300 - DMA General Status Register */
-       char    res22[3324];
+       char    res2[3324];
 } ccsr_dma_t;
 
 /* tsec1-4: 24000-28000 */